Network Analysis Laboratory

Appendix 1: Breadboarding

A1.1 Background In the laboratory, electronic circuits are often connected in a temporary fashion in order to facilitate

testing. This type of construction is called breadboarding. Circuits built using a breadboard technique often do not perform as well as those constructed in a more compact and permanent form (e.g., on a printed circuit board). In breadboard construction, however, it is easier to alter the circuit for experimentation. This section will describe potential problems with breadboard construction and suggest ways to mitigate them.

A popular device for breadboarding with integrated circuits is called a solderless breadboard, and a typical one is shown in Figure A1. The breadboard has a grid pattern of holes into which wires, component leads, or integrated circuit (IC) pins may be inserted. Each hole is an electrical connection point, and the holes are electrically connected according to a pattern. A typical connection pattern is shown in the figure. The vertical rows of 5 connected holes do not connect across the center gap. Two or more wires or component leads inserted into the same connecting row are electrically connected together. For example, the figure shows an 8-pin IC inserted in the breadboard. Anything inserted into the same vertical row as pin 8 of the IC will be electrically connected to that pin. Long rows at the top and bottom can be used to make many connections to the same node from different locations on the breadboard (e.g., to a power supply or ground bus). On many breadboards, the long rows are connected all the way across, but some of them break the long rows in the center.

A1.2 Practical Circuits A practical circuit (i.e., a circuit constructed with real components) contains parasitic elements.

These elements are not deliberately put into the circuit, but are present because of the physical properties of the materials used to construct the circuit and its components. Parasitic capacitances exist between two conductors separated by an insulator, parasitic resistances are present due to finite conductance of wires and contacts, and wires have self and mutual inductance.

In solderless breadboards, parasitic capacitances are present between adjacent rows, and from each row to ground if the breadboard is mounted on a metal surface. These capacitances are on the order of a few picofarads. Parasitic series resistances on the order of one ohm occur at each connection point. Wires used to make connections have a series inductance of about 15nH per centimeter (about 40nH per inch), and mutual inductances exist between wires.

Breadboarded circuits in general have especially high parasitic element values, and these can cause problems during testing. Some of the more common problems are described below.

Parasitic elements often create low-pass filters, which degrade the high-frequency performance of amplifiers. It is often possible to ignore such high-frequency loss and do useful testing at lower

Connected Rows

May or may not be connected here (see text)

Four empty holes connect to IC pin 8

Center gap

Figure A1. A Solderless Breadboard.

frequencies. If a parasitic low-pass filter occurs within a feedback loop, however, the added phase shift may make the loop unstable. Instability implies that the circuit will oscillate (i.e., it will produce signals even if there is no input). The circuit must be stabilized before any useful testing can be done.

Schematic diagrams typically show numerous connections to ground. Ideally, all of these connections are at ground potential. Between each connection to ground, however, parasitic series inductances and resistances exist. Therefore as signal currents flow from one ground connection to another, small voltages are developed between the connection points. The same is true for connections to power supply nodes. When imperfect connections to ground or power supplies are shared, unintentional signal paths are created. In other words, parts of the circuit that are supposed to be isolated from each other will interact. The unwanted signal paths can be another cause of circuit instability.

A1.3 Standard Practices Carrying out a complete circuit analysis including all parasitic elements is often not practical for hand

calculations. Indeed, integrated circuit (IC) designers use specialized computer programs to determine parasitic element values from the IC layout, and then include the parasitics in SPICE simulations. For breadboarded circuitry, it is preferable to follow certain standard practices that minimize the effects of parasitic elements.

The following are principles of good breadboarding technique: • Avoid using wires that are unnecessarily long. (It is not necessary to force wires to follow right-

angle paths as in drawn schematic diagrams.) • Avoid using more connection points (tie points) than necessary. • Try to make all ground connections to a single, low-resistance bus (e.g., only one row of a solderless

breadboard). • To the extent possible, keep amplifier outputs physically separated from amplifier inputs. • Do not use solderless breadboards for high frequency (e.g., radio frequency) circuits. If a high-

frequency circuit must be breadboarded, construct the circuit using point-to-point soldering above a ground plane. A piece of new (i.e., not etched) printed circuit board material will provide a good ground plane.

• Always use power supply bypass capacitors (see below).

A1.4 Power Supply Bypass Capacitors The creation of undesirable signal voltages on the power supply busses can be greatly reduced by the

use of power supply bypass capacitors. These are placed physically near sensitive circuitry. In many cases, bypass capacitors are not optional, but necessary. Bypass capacitors are not just for breadboards; they are used on printed circuit boards (e.g., at each IC package on a printed circuit board). IC designs sometimes include bypass capacitors on the silicon chip itself.

Figure A2 shows the basic principle of power supply bypass capacitors. The power supply voltage is connected to the load through long wires that each have resistance R and an inductance L. The load current may have constant part, but here we are concerned with the time-varying (ac) part called ( )i t . When the bypass capacitor BC is not used, the ac load current must flow through the large loop. In this case, voltage

drops will develop across the parasitic resistances and inductances, and the load voltage will contain a significant time-varying part. This situation can cause problems, especially if more than one load shares

VSUPPLY CB i t( )

R

R L

L

Small Loop (with CB)

Large Loop

(without CB) VLOAD

Figure A2. Circuit with long power supply leads.

the same long wires to the supply voltage. In that case, the current of one load will affect the voltage across the other and vice versa. The addition of BC will help by reducing the size of the ac current loop and the number of elements it contains.

A good rule for breadboarding is to always use at least one 0.1 Fµ bypass capacitor between each power supply and ground on the breadboard. It may be necessary to use one capacitor for each supply at each block of circuitry or at each chip. Bypass capacitors should be good high-frequency capacitors such as disk ceramic or monolithic ceramic.

A1.5 Examples Figure A3 shows a simple operational amplifier (op-amp) circuit that is to be breadboarded. This

schematic shows the pin numbers of the integrated circuit, and includes the power supply pins and their bypass capacitors. Normally, the pin numbers are not shown because they can be found in the data sheet for the type of op-amp used. The power supply connections and bypass capacitors are normally not shown in order to keep the schematic neat.

Figure A4 shows an example of breadboard construction (of the circuit of Figure A3) with a poor construction technique. The figure has the following numbered notes:

1) Extra connection points are used for the feedback resistor fR . 2) An extra-long wire is used to connect the inverting input of the op-amp to fR . 3) An extra-long wire is used to connect the non-inverting input of the op-amp to ground. 4) An extra connection point is used for 1BC . 5) Input and output connections are physically close. As a general rule, input connections should

be separated from output connections. If this is a unity-gain stable op-amp, then it's probably OK for the inverting input to be near the output.

In some situations, it may not be necessary (or even possible) to avoid every flaw described above. For example, the technique shown in Figure A4 might be acceptable for low-frequency testing with a 741 op-amp. It should be noted, however, that problems due to poor technique tend to have a cumulative effect in larger circuits. The best construction technique should be used wherever possible.

2

3 6

7

4

INV OUTV

10V+

10V−

R f

Ri CB1

CB2

Figure A3. Example Circuit.

IC

+10V bus

-10V bus GND bus

1

2

3

4

OUTV

INV

5

Figure A4. Poor technique.

An example of the same circuit with better breadboarding technique is shown in Figure A5. The notes for the figure are as follows:

6) The feedback resistor fR is connected directly from pin 2 to pin 6 with no extra connection points. The resistor can be physically placed above the IC package.

7) A short wire is used to connect the non-inverting input to ground. 8) The bypass capacitors go to ground via the shortest, most direct path. This is not always

possible. 9) The input is separated from the output.

IC

+10V bus

-10V bus GND bus

INV

OUTV

6

7

8

9

Figure A5. Good technique.