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Q1.) Using the circuit diagram below, draw a timing diagram that shows the output of the multiplexer as a sequence of A’s and B’s. Show the output sequence for eight full clock cycles.

( Q’ )

Q2.) Use D Flip Flops, a decoder and logic gates to design an asynchronous counter that counts down from 6 to 2.

Q3.) Design the following three counters. Use T Flip Flops in the design. Show the characteristic table, transition table, next state table and K-maps for the design as well as the logic diagram of the design.

A.) A synchronous up counter that counts from 0 to 7. B.) A synchronous down counter that counts from 7 to 0.

C.) A synchronous 3 bit up/down counter. Use a single bit to control the direction of the count.

Q4.) Design the sequential circuit defined by the following state diagram. Use D Flip Flops in the design. Show the characteristic table, transition table, next state table and K-maps for the design as well as the logic diagram of the design.