Advance power electric design project

192 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Single-Stage High-Efficiency 48/1 V Sigma Converter With Integrated Magnetics

Mohamed H. Ahmed , Student Member, IEEE, Chao Fei , Student Member, IEEE, Fred C. Lee , Life Fellow, IEEE, and Qiang Li , Member, IEEE

Abstract—A high-efficiency, high-power-density Sigma converter for a 48 V rack architecture in data centers is proposed in this paper. The Sigma converter is a quasi- parallel converter that uses a high-efficiency unregulated converter to deliver the bulk power to the load. A small buck converter is responsible for regulating the output volt- age with prescribed dynamic responses. A design guideline for Sigma converter with integrated magnetics is provided in this paper. The unregulated converter is an LLC con- verter designed with a printed circuit board (PCB) winding matrix transformer, a structure which integrates four ele- mental transformers into one core. The buck converter is designed with discrete gallium nitride (GaN) devices and a PCB winding inductor. The proposed Sigma converter op- erates at 48 V input and 1 V-80 A output and can achieve a power density of 420 W/in3 as well as a peak efficiency of 94%.

Index Terms—48 V voltage regulator module (VRM), integrated magnetics, matrix transformer, Sigma converter.

I. INTRODUCTION

D UE TO the ever increasing load demands of data centersand telecommunication applications, a 10% share of the total power consumption by 2020 [1] is predicted. These needs are driving the power management solutions for increased efficiency and power density. To fulfill digital content demands, multicore processors with a greater number of cores and power- hungry processors are increasing every year. With increasing demands of high current (>220 A) at low voltage levels (<1.85 V) for each CPU [2], the power consumption per server rack is reaching 15 kW. This raises attention toward a more efficient system architecture in the rack level. Traditionally, data centers the system architecture as shown in Fig. 1(a) with a 12 V bus backplane, thus, resulting in poor overall power delivery efficiency due to the large distribution loss at the 12 V bus. Shifting to higher bus voltages, 48 V instead of 12 V, was proposed [3], and subsequently adopted, by Google as shown in Fig. 1(b), where the uninterruptible power supply (UPS)

Manuscript received March 25, 2018; revised July 10, 2018, August 28, 2018, and November 15, 2018; accepted January 6, 2019. Date of publication February 5, 2019; date of current version August 30, 2019. (Corresponding authors: Mohamed H. Ahmed and Qiang Li.)

The authors are with the Center for Power Electronics Systems, Virginia Polytechnic Institute and State University, Blacksburg, VA 24061 USA (e-mail:, [email protected]; [email protected]; fclee@vt. edu; [email protected]).

Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TIE.2019.2896082

Fig. 1. Data centers distribution system: (a) traditional ac distribution; (b) dc distribution with 48 V bus.

systems are replaced by a local dc 48 V battery backup [4]. Significant challenges rise with that proposed architecture. The 48 V voltage regulator module (VRM) located in the vicinity of the CPU has to be designed with very high efficiency and high power density [5].

A great amount of work has been done with the 48 V VRM for both data center and telecommunication applications. They can be categorized as one-stage and two-stage solutions.

A two-stage 48 V VRM is the first commercially avail- able solution by Vicor [3], [6]. Their soft-switched first-stage buck-boost preregulator module (PRM), cascaded with a soft- switched unregulated sine amplitude voltage transformation module (VTM), enables their solution to achieve high efficiency and high density. However, the solution is not easily scalable as designed in high current levels (>100 A/module). Another two- stage approach was used in [5], [7], and [8], with an unregulated inductor-inductor-capacitor (LLC) dc–dc transformer (DCX) as the first stage and a conventional multiphase regulated buck converter for the second stage. This solution reported a high ef- ficiency and high density with significant improvement for light load efficiency. The two-stage architecture was proposed in [4] and [9], replacing the isolated bus converters with a resonant switched capacitor circuit that can achieve a high efficiency of 98.2% and power density of 500 W/in2 for the first stage converter; however, there is no reported two-stage efficiency or power density for the 48/1 V conversion. Another state-of-art product was proposed by STM Microelectronics [10] based on a single-stage quasi-resonant converter with a current-doubler rectifier reported in [11] and [12]. The converter can operate with zero voltage switching (ZVS) in all loading conditions with a high efficiency of 93%. However, the topology requires four magnetic components, reducing the converter power density. In

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 193

Fig. 2. Sigma converter structure.

[13]–[15] a current-tripler 48 V VRM with a compact mag- netic structure was proposed, together with a 1-MHz self-driven scheme that solves the problem of synchronous rectifier (SR) switching and can achieve very high efficiency at high-frequency operation. However, in the proposed scheme not all the primary side switches can achieve ZVS at light load, resulting in a sig- nificant efficiency drop during light loading conditions.

The Sigma converter concept was first proposed in [16] and [17], for 12 V VRMs that exhibited outstanding performance over multiphase buck converters. The same architecture was later used in different applications [18], [19] demonstrating a very efficient operation. In this paper, the same concept was revisited and proposed for a single-stage 48 V VRM [20]. The Sigma converter is a quasi-parallel converter that connects two converters in series from the input side, and in parallel from the output side. One of the converters is an unregulated isolated DCX that conducts the bulk power, while the other is a non- isolated converter responsible for regulating the output voltage (D2D), as shown in Fig. 2. A potential benefit of this architecture is its ability to achieve higher conversion efficiency.

Further efforts should be made for the design of the DCX and D2D to maximize the benefits of this power architecture. The soft switching properties of the LLC converter enables operation at a very high frequency to achieve high density while achieving high efficiency, making it a suitable candidate for this converter’s DCX. Integrating magnetics with PCB winding and matrix transformer with the opportunity of flux cancellation has been reported [21]–[27] to reduce the size and losses of the LLC DCX transformer at high-frequency operation.

None of the preceding work has discussed the Sigma con- verter design with integrated magnetics even though the matrix transformer structure and design will impact the performance of this converter significantly as will be discussed in the following sections. In this paper, a detailed design guideline for the Sigma converter with integrated magnetics will be discussed by which the right matrix transformer structure can be chosen for differ- ent input/output voltage variations to maximize the benefits of this conversion system. A novel matrix transformer which inte- grates four elemental transformers into one core structure with printed circuit board (PCB) windings is proposed to achieve high efficiency and power density. Accompanying the DCX is a buck converter with PCB winding inductor to realize all the stringent requirements for regulation dynamics while increasing the power density.

TABLE I PROPOSED CONVERTER SPECIFICATIONS AND LLC-DCX TURNS RATIO

DESIGN RANGE

This paper is organized as follows. Section II presents the design principle of the Sigma converter architecture with inte- grated magnetics. Section III discusses the optimal design of the LLC-DCX with a PCB winding matrix transformer. Section IV optimizes the design of the buck converter with a PCB wind- ing inductor. Section V presents the converter prototype and the experimental results. Section VI concludes this paper.

II. DESIGN GUIDELINE OF SIGMA CONVERTER WITH INTEGRATED MAGNETICS

In the Sigma architecture, both converters have the same input current, thus, the power sharing between them is proportional to the input voltage across each of them as in (1). In the proposed architecture, the DCX converter is an LLC converter operating at resonant frequency, utilizing the matrix transformer’s leak- age inductance to form the resonant tank with the addition of resonant capacitor. The small leakage inductance of the matrix transformer will result in a large Ln = Lm /Lr resulting in a constant gain LLC converter that does not change much with frequency variation. As a result, the input voltage of the DCX will be the output voltage of the converter multiplied by the DCX turns ratio n and the remaining voltage will appear on the buck-D2D as given in (2). The DCX turns ratio n has a signifi- cant role in the voltage distribution across these two converters and consequently, the power sharing among them. For efficient power conversion, the LLC-DCX is required to handle most of the power as it can be designed with very high efficiency com- pared to the buck-D2D; the condition VDCX � VD 2D should be satisfied in order to achieve that goal.

The Sigma architecture has two main design constraints— the first constraint is to achieve high efficiency of operation by limiting the maximum allowable voltage appearing on the buck converter during all operating conditions, this constraint limits the minimum allowable turns ratio as given in (3). The second constraint is to ensure a positive voltage across the buck converter that is always higher than the maximum output voltage by which the duty ratio is always (D < 1) and this condition is given by (4) and sets the maximum allowable turns ratio. Vinm in , Vinm ax , Vom in , Vom ax are the maximum and minimum input and output voltages, respectively, Dm ax is the maximum buck duty ratio, and Vbuckm ax is the maximum stress on the buck converter.

Different applications will require a specific design of this architecture based on the constraints mentioned above. The pro- posed converter specifications and the turns ratio design range are listed in Table I. The maximum allowable voltage across the buck converter is set to be Vbuckm ax < 30 V , this will allow

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194 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 3. (a) Basic matrix transformer structure with multiple elemental transformer. (b) Primary winding implementation with PCB winding.

using low voltage devices for the buck converter to maximize its efficiency and maintain the bulk power to flow through the LLC-DCX in all operating conditions

PDCX /PD 2D = VDCX /VD 2D (1)

VDCX = nVo VD 2D = Vin − nVo (2)

nm in > Vinm ax − Vbuckm ax

Vom in (3)

nm ax < Vinm in Vom ax

− 1 Dm ax

. (4)

Although the maximum turns ratio (nm ax = 43) will result in the most efficient operation, the implementation of specific turns ratio with matrix transformer is constrained by other limiting factors. First, the matrix transformer with core simplification and integration by the flux cancellation method has been proposed in [21] and [25] by which two elemental transformers can be integrated using a single UI-core, resulting in significant core loss and footprint reduction. This means that we always need an even number of elemental transformers (2, 4, 6, . . . , etc.) in order to take the advantage of flux cancellation and core integration for high efficiency and power density.

Second, the basic structure of matrix transformer with multiple elemental transformers is shown in Fig. 3(a), where the single transformer is divided into multiple elemental transformers connected in series from the primary side and in parallel from the output side. To ensure equal current sharing between these elemental transformers, the number of turns in each elemental transformer should be equal, i.e., (nTR1 = nTR2 = . . . = nTRN ). Third, with the requirement of multiple turns per elemental transformer (nTRx > 1), these turns should be implemented in more than one layer in order to have an entrance and exit path for the primary side current without using extra via or PCB layers as shown in Fig. 3(b). Finally, the number of primary turns per PCB layer should be equal in order to maintain a balanced magnetomotive force (MMF) across the transformer winding and ensure perfectly interleaved primary and secondary windings to reduce all ac-related winding loss.

Applying these four PCB winding implementation related constraints to the design specifications and architecture constraints listed in Table I will result in all the design options

TABLE II LLC-DCX WITH MATRIX TRANSFORMER OPTIONS FOR SIGMA CONVERTER

WITH DIFFERENT PRIMARY SIDE CONFIGURATIONS

Fig. 4. Proposed 48/1 V-80 A Sigma converter structure.

listed in Table II, where, NE is the number of elemental trans- formers, nTR is the turns ratio of each elemental transformer, and ntotal = NE × nTR is the LLC-DCX total transformer ratio.

It is clear that different matrix transformer and primary side configurations will have different impact on the Sigma converter operation, the first and last options NE = 4 and NE = 10 will result in the highest possible converter efficiency with the high- est power flowing through the LLC-DCX. Although both have the same impact on the architecture, for simplicity of the design, the first option (NE = 4 )was chosen for this design, the case with NE = 10 can be a possible candidate if a higher current converter is required. Although half bridge (HB) configuration have lower turns ratio, it requires more PCB layers compared to the full bridge (FB) configuration to implement the PCB wind- ing, so FB was selected to reduce the cost and complexity of the proposed converter. The proposed Sigma converter structure is shown in Fig. 4, the total DCX turns ratio is n = 40 : 1. The benefits of this design can be shown from the power-sharing graph in Fig. 5. At most operating conditions, the LLC-DCX handles most of the output power by which higher overall ef- ficiency is expected. The same design guidelines can be used for other 48 V VRMs with different input and output voltage and power requirements to select the optimal matrix transformer structure for each application. The optimization of this matrix transformer will be discussed in the following section to achieve the highest possible efficiency and power density.

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 195

Fig. 5. Power sharing between the LLC-DCX and the buck-D2D.

III. LLC CONVERTER WITH MATRIX TRANSFORMER DESIGN AND OPTIMIZATION

The design of LLC-DCX for high output current and low output voltages is very challenging. The necessity of paralleling multiple SRs to handle this high output current results in cur- rent sharing problems and large transformer termination losses, a practice that should be avoided if possible. The concept of the matrix transformer is to employ various elemental transformer arrays interwired to form a single transformer. This will re- duce the total transformer losses by splitting the current among various elemental transformers and in the same time achiev- ing flux cancellation wherever possible. The matrix transformer has exhibited an outstanding performance when used in various applications. In addition to minimizing termination losses, the simple PCB winding implementation makes it suitable for this application, where high output current of the LLC-DCX is re- quired. In this section, the design and optimization of the matrix transformer for the LLC-DCX will be discussed in detail.

A. Integration of LLC-DCX Matrix Transformer Structure and PCB Winding Implementation

For the proposed Sigma converter, the LLC-DCX requires a transformer with (40:1) turns ratio. This single transformer was broken into four elemental transformer arrays as shown in Fig. 6, where the transformer leakage and magnetizing in- ductances with an additional capacitor are used to form the resonant tank of the LLC-DCX. The primary windings of this structure are connected in series while the secondary windings are connected in parallel. Hence, there would be no current shar- ing problem between paralleled secondary windings or SRs. To further reduce conduction losses, the proposed structure par- allels only two SRs at each secondary winding. Transformer termination is the physical connection between the transformer windings and the corresponding primary and secondary devices. They contribute to a large portion of the transformer losses when operating at high switching frequencies [21]. The matrix trans- former structure helps split the output current among different transformer outputs, thus reducing conduction and termination losses significantly.

Fig. 6. Proposed LLC-DCX with matrix transformer.

A potential drawback of the matrix transformer approach is the increased footprint and core loss due to the increased number of magnetic cores. By operating at very high switching frequen- cies, the magnetic core size can be reduced. To achieve high power density, the complex four-transformer structure shown must be simplified. Originally, the four elemental transformers each utilize a separate UI-core as shown in Fig. 7(a). By rear- ranging the four transformers in a way that two transformers are on the top side (TR1 and TR2) and two on the bottom side (TR3 and TR4) we can integrate the four transformers with one core structure with a wide center leg as the return flux path of each elemental transformer as in Fig. 7(b). By reversing the cur- rent direction in TR3 and TR4, the flux in the wide center leg will be in opposite directions and cancel each other, reducing the total core loss and allowing the removal of this center leg without scarifying any winding or core loss. Hence, the four transformers can be integrated into one core structure with four transformer pillars, which can be easily manufactured, saving a significant amount of space and core loss as shown in Fig. 7(c). The proposed integration method not only helps with the reduc- tion of the core loss and footprint but also helps in achieving a perfectly current sharing between all the transformer secondary windings. Integrating the four transformers into a single core structure helps achieve a symmetrical air gap for all the four el- emental transformers. Although the four primary windings are connected in series, each elemental transformer will see a differ- ent magnetizing inductance determined by its own air gap; any asymmetry in the magnetizing inductances between these ele- mental transformers will create a current unbalance between the secondary windings as well. With the single core structure, the tolerance in these air gaps can be well-controlled to avoid these problems when compared to using two single UI-cores [25].

The proposed matrix converter is implemented with a 14-layer PCB and 2 oz copper for each layer. The detailed PCB winding arrangement is shown in Fig. 8, the yellow arrows indicate the current directions in the positive half-cycle. Layers 1 and 14 are

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196 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 7. Derivation of proposed matrix transformer: (a) original four ele- mental transformer structure with separate UI-cores; (b) rearranged four elemental transformers integrated in one core with a wide center leg; and (c) integrated matrix transformers with one core structure without center leg.

used to place the SRs and the output capacitors. Each set of paral- lel SRs have one device on Layer 1 and the other device on Layer 14. These devices and capacitors are then connected to the cor- responding secondary winding through vias. This arrangement helps reduce the termination connections between windings and SRs, while splitting the termination current into two layers. This reduces termination losses significantly. Layers 3 and 6 are one set of primary windings. In each layer, five turns are wrapped around each core pillar and then both layers are connected in se- ries, totaling the required 40 turns. A parallel connection is made with Layers 9 and 12, which is another set of primary windings to reduce conduction losses. The remaining layers are for the center-tap secondary windings. Each layer has one turn, and all layers are in parallel, to reduce conduction losses. The primary and secondary windings are perfectly interleaved to reduce the ac losses due to the proximity effect as shown in Fig. 8(b).

B. Matrix Transformer Design Optimization

To optimize the matrix transformer design, the tradeoff be- tween total transformer losses and the footprint is evaluated, and then the optimal switching frequency is selected. First, the im-

Fig. 8. PCB winding arrangement of the proposed matrix transformer: (a) Layers 1&14 for SRs and output capacitors. (b) 14 layer PCB arrangement. (c) Layers 3 and 9 for primary#1 windings. (d) Layers 6 and 12 for primary#2 windings. (e) Layers 2, 5, 8, and 11 for secondary#1 windings. (f) Layers 4, 7, 10, and 13 for secondary#2 windings.

TABLE III CORE SHAPE IMPACT ON WINDING LOSS

pact of the core pillar shape on the winding losses was evaluated. A rectangular core versus a circular core pillar was evaluated by finite-element analysis (FEA) simulations; both cases have the same core area and winding width. The results in Table III show a 16–22% winding loss reduction with the circular post due to the shorter current path length. Secondly, various high frequency magnetic materials were previously surveyed in [5] and the results showed that the ML-91 from Hitachi shows the lowest core loss density for this high-frequency operation and therefore, it was selected for the proposed LLC-DCX converter.

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 197

Fig. 9. Transformer total losses and footprint at 1.5 MHz and full load.

Fig. 10. Transformer losses variation with switching frequency. (a) Winding loss. (b) Core loss.

The design optimization of matrix transformer has been dis- cussed in previous literature [23]–[25] for 400/12 V converters, the total transformer loss is calculated at the optimal footprint and then a design point is selected as a tradeoff between effi- ciency and power density. The same design methodology was used for this transformer by adding a new design parameter, which is the operating switching frequency; the total trans- former losses versus optimal footprint at full load and nominal voltage conditions at 1.5 MHz switching frequency are shown in Fig. 9. Due to the low output voltage and high frequency, the volt·second applied on the core is very small, and the winding losses are more dominant with very small core losses.

With lower switching frequencies, the ac related winding loss will reduce, while the core loss increases due to the higher volt·second as shown in Fig. 10. From the results in Fig. 11, the total losses are highest at high switching frequencies, when reducing the frequency, a reduction in the total losses occurs until 1 MHz is reached. This is because the reduction in the winding losses is counteracted by a significant increase in the core losses, so further reducing the switching frequency will result in a higher total transformer loss.

To achieve high efficiency and power density, the design re- gion is highlighted in Fig. 11. The corresponding total loss vari- ation with different switching frequencies was plotted as shown in Fig. 12. With different footprints, the total losses tend to have a minimum loss point at 1 MHz switching frequency; therefore, 1 MHz was selected as the operating frequency. The efficiency of the converter was then calculated, and the final design point

Fig. 11. Transformer total loss versus footprint at different switching frequencies.

Fig. 12. Transformer total losses versus switching frequency.

Fig. 13. Transformer fringing flux impact. (a) Cross-sectional view of fringing flux distribution. (b) Current distribution in Layer 1. (c) Current distribution in Layer 14.

was selected at a footprint of 300 mm2, since after that point, the increase in the converter efficiency is marginal.

The magnetizing inductance of the transformer is created by adding an air gap between the core pillar and the magnetic plate. A great amount of fringing flux will spread through the air gap creating many eddy current losses in the nearby layers. This could be severe for the designed transformer. The fringing flux at the air gap was simulated using ANSYS Maxwell and the results shown in Fig. 13 show the strong fringing flux at the air gap of one of the four elemental transformers. Layer 14, which is closer to the air gap, handles the same amount of current, but has ten times more losses than Layer 1. This is due to the

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198 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 14. Total transformer losses versus extending the core air gap.

TABLE IV PARALLEL LAYER CURRENT DISTRIBUTION

strong fringing flux. To solve this issue, the air gap needs to be pushed away from the PCB layers by a distance hf r . Using FEA simulation, different hf r values were evaluated, and the results are shown in Fig. 14. The total loss reduced significantly with the higher hf r , until reaching a diminishing return point at hf r = 0.6 mm, which was chosen in the final design.

In the proposed PCB winding arrangement shown in Fig. 8(b), we have two primary parallel layers and four secondary winding parallel layers. Although we minimized the losses due to the fringing flux, it tends to attract the current to the layers close to the transformer air gap resulting in an unbalanced current sharing as listed in Table IV. This issue has not been addressed in this paper and more analysis needs to be done in order to have perfect current sharing between layers.

IV. BUCK CONVERTER DESIGN OPTIMIZATION WITH PCB WINDING INDUCTOR

The Sigma converter was designed so that most of the power flows through the higher efficiency LLC-DCX while the buck converter is responsible for regulating the output voltage. From Fig. 5, it is clear that the power and voltage applied to the buck converter is variable, depending on the operating condition. In the worst case (Vo = 0.8 V and Vin = 55 V), the buck con- verter will experience a voltage stress of (Vbuckm ax = 23 V) and should handle a current of about (33 A), so devices with a minimum voltage rating of 40 V are required for the buck con- verter. Low voltage gallium nitride (GaN) devices have shown an outstanding performance compared with silicon devices. In this design, the high side switch is EPC2015c while the low voltage switch is EPC2024. An optimal layout presented in [28] was used for the layout of the discrete GaN devices to minimize the effect of parasitic inductances and their effect on switching related losses. The inductor design for this buck converter is

Fig. 15. Proposed single-turn PCB winding inductor structure: (a) top view and (b) cross sectional view.

Fig. 16. Measured efficiency of buck converter with discrete inductor and PCB winding inductor.

important to achieve high power density and high efficiency. For low voltage buck converters, the common practice is using a commercial discrete inductor that has a very low dc resistance (DCR) and low core loss. However, these inductors have a large footprint and high profile, which reduces the overall converter power density significantly.

In this proposed Sigma converter, the LLC-DCX uses a 14-layer PCB to implement the DCX transformer. The same PCB can be utilized to implement a single-turn inductor. As the PCB copper thickness is smaller than the copper foil thickness used by discrete inductors, the inductor windings can be parallel connected in multiple layers, to reduce the total inductor DCR. The basic structure of the proposed PCB winding inductor is shown in Fig. 15. An EI-core shape with ML-95 material from Hitachi was used to implement the single-turn inductor. An in- ductance of L = 190 nH and a DCR of RDC = 0.53 mΩ are achieved. Although the DCR in the proposed design is larger than the commercial discrete inductors, the efficiency reduc- tion is negligible since the buck converter is only handling a small amount of output current. Using this PCB winding induc- tor will help achieve high power density without scarifying the efficiency. A buck converter with commercial discrete inductor and PCB winding inductor was experimentally evaluated. The measured efficiency shown in Fig. 16 shows that the buck con- verter with PCB winding inductor has higher efficiency in most operating regions.

The reason for this is the lower core loss of the designed PCB winding inductor; the ac-related loss of the PCB winding in- ductor was evaluated using ANSYS Maxwell. The commercial inductor used is from Würth Elektronik, and the ac-related loss of this inductor was calculated based on the inductor loss cal- culator software REDEXPERT. It can be shown from Table V that the ac-related losses of the PCB winding inductor is three times lower than that of the commercial inductor. These losses

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 199

TABLE V COMPARISON BETWEEN PCB WINDING AND COMMERCIAL INDUCTOR

Fig. 17. Current distribution in the PCB layers of the inductor.

Fig. 18. Sigma converter prototype: (a) top view and (b) side view.

include both RAC and core loss where both are load indepen- dent and only determined by the peak to peak current ripple which can be reflected by the light load efficiency increase in the efficiency results when using PCB winding. The volume of the PCB winding inductor is 25% smaller than the commercial inductor but it has almost double the value of the DCR whose losses dominate at higher loading conditions; that explains why both solutions have the same efficiencies at heavy load. The reason for the high DCR can be shown from Fig. 17; noneven current sharing between all parallel inductor PCB layers occurs resulting in the increased DCR value.

V. EXPERIMENTAL RESULTS

The prototype of the proposed 48 V Sigma converter VRM with integrated magnetics is shown in Fig. 18. The LLC-DCX has four output terminals, two on each side of the PCB, while the buck converter has one output terminal. The prototype also includes a microcontroller (MCU) for control of this converter. The proposed converter can achieve a high power density of 420 W/in3 in a very low profile of 4 mm which is much bet- ter than any state-of-art solution. The parameters of the pro- posed converter are listed in Table VI. Even with a total primary winding of 40 turns, the transformer has leakage inductance of

TABLE VI SIGMA CONVERTER PARAMETERS

Fig. 19. Sigma converter operating waveforms: (a) input voltage of 48 V and 1 V-80 A output and (b) input voltage of 55 V and 0.8 V-80 A output.

180 nH, this is due to the interleaving structure between primary and secondary windings that helps cancel all the transformer leakage flux.

The converter steady-state operating waveforms at heavy load condition and nominal input voltage and output voltages (48/1 V) is shown in Fig. 19(a). VQ 1LLC is the drain-source voltage of Q1 switch in LLC-DCX, IL r is the resonant cur- rent in LLC-DCX, VSW Buck is the switching node voltage for buck converter, and VSR LLC is the drain-source voltage of SR in LLC-DCX. The LLC-DCX primary and secondary side de- vices can achieve zero voltage switching. The primary turn-OFF current is very small so that the turn-OFF losses can be mini- mized. The overshoot at the buck converter switching node is very small, showing the effectiveness of the optimized layout of the GaN devices.

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200 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Fig. 20. Sigma converter SRs drain to source voltage waveforms.

Fig. 21. Sigma converter thermal image: (a) input voltage of 48 V and 1 V-80 A output and (b) input voltage of 55 V and 0.8 V-80 A output.

The case with high input voltage and lowest output voltage is shown in Fig. 19(a), the buck switching node voltage is high- est and the duty ratio is smallest. In this condition, the buck converter is delivering its highest power; soft switching is still achieved with a clean buck converter voltage although it oper- ates at very large input voltage and high output current. The importance of integrating the four elemental transformers with a single core can be seen from Fig. 20. All the SR drains to source voltages are perfectly aligned despite being on different magnetic flux paths; this indicates the symmetry of the air gap across each elemental transformer that can easily be realized us- ing a single core structure compared to multiple core structures that are more susceptible to tolerance variations.

The thermal images at nominal condition and full load with 300 LFM air cooling are shown in Fig. 21(a). It is clear that there are no hot spots for the proposed converter; even the power den- sity is much higher than that of state-of-art designs. The thermal image of the least efficient case (55/0.8 V) is shown in Fig. 21(b); it is clear that the buck converter temperature is getting higher and represent the hot spot of the converter, however, the maxi- mum temperature is below 70 degree. The DCX efficiency was measured separately at the nominal condition and compared with the analytically calculated efficiency, the results shown in Fig. 22 show a good agreement between the estimated and measured efficiency validating the loss analysis and simulations used for the transformer optimization. The variation at light load efficiency is caused by underestimating the turn-OFF loss of the primary side devices, which can only be obtained from Spice simulations that are not very accurate. The converter efficiency at different conditions is shown in Fig. 23. The proposed con- verter can achieve a peak efficiency of 94% that drops to 92.6%

Fig. 22. Experimental efficiency measurement of LLC-DCX and com- parison with estimated efficiency.

Fig. 23. Sigma converter measured efficiency.

TABLE VII COMPARISON OF PROPOSED CONVERTER WITH STATE-OF-ART SOLUTIONS

at full load condition. The closed loop control of the proposed converter has been discussed in detail in [30] and is beyond the scope of this paper.

A comparison between the performance of the proposed 48 V Sigma converter and other state-of-art solutions is listed in Table VII. It should be noted that all the power densities are without any control or auxiliary power supply circuitry. The Sigma converter can achieve the highest conversion efficiency compared to all other state-of-art solutions, Vicor’s solution can achieve the highest power density, however, the proposed Sigma converter with integrated magnetics can be designed in a much smaller profile.

VI. CONCLUSION

In this paper, a 48 V Sigma converter VRM was proposed for the power architecture in server and data centers with 48 V

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AHMED et al.: SINGLE-STAGE HIGH-EFFICIENCY 48/1 V SIGMA CONVERTER WITH INTEGRATED MAGNETICS 201

rack voltage. The proposed Sigma converter was a quasi-parallel converter that uses a high-efficiency LLC-DCX to deliver 80% of the load, and a buck converter to regulate the output volt- age with a small amount of power during nominal condition so that higher conversion efficiency could be realized. A de- sign guideline for Sigma converter with integrated magnetics was presented to ensure that high efficiency and power density could be achieved. A novel matrix transformer structure was proposed for the LLC-DCX to integrate four transformers into one core structure to handle large output current, and a 14-layer PCB winding implementation was employed. To reduce the total transformer losses, the optimization for this transformer was discussed, and a design methodology was provided. A buck converter with a single-turn PCB winding inductor was also pre- sented. A hardware prototype was built for the proposed Sigma converter and it demonstrated a peak efficiency of 94%, a full- load efficiency of 92.5%, and a power density of 420 W/in3 in a very low profile of 4 mm. The proposed converter exhibited a significant increase in the efficiency and power density over the state-of-art solutions with very good thermal performance.

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Mohamed H. Ahmed (S’16) received the B.S. and M.S. degrees in electrical engineering from Cairo University, Cairo, Egypt, in 2010 and 2014, respectively. He is currently working toward the Ph.D. degree with the Center for Power Elec- tronics Systems, Virginia Tech, Blacksburg, VA, USA.

His main research interests include high-frequency conversion systems, resonant converters, voltage regulator modules, and high-frequency magnetic designs.

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202 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 67, NO. 1, JANUARY 2020

Chao Fei (S’13–M’18) received the B.S. degree in electrical engineering from Zhejiang Univer- sity, Hangzhou, China, in 2012, and the M.S. and Ph.D. degrees in electrical engineering from the Center for Power Electronics Systems (CPES), Virginia Tech, Blacksburg, VA, USA, in 2015 and 2018, respectively.

He is now a Hardware Engineer at Google Inc., Mountain View, CA, USA. His research interests include high-frequency power conver- sion, resonant converters, digital control, power

management and wireless charging.

Fred C. Lee (S’72–M’74–SM’87–F’90–LF’12) received the B.S. degree in electrical engi- neering from National Cheng Kung University, Tainan, Taiwan, in 1968, and the M.S. and Ph.D. degrees in electrical engineering from Duke Uni- versity, Durham, NC, USA, in 1972 and 1974, respectively.

He is currently a University Distinguished Pro- fessor with Virginia Tech, Blacksburg, VA, USA, and the Director of the Center for Power Elec- tronics Systems (CPES), a National Science

Foundation Engineering Research Center (NSF ERC) established in 1998, with four university partners—University of Wisconsin-Madison, Rensselaer Polytechnic Institute, North Carolina A&T State University, University of Puerto Rico-Mayaguez, and more than 80 industry mem- bers. During his tenure at Virginia Tech, he has supervised to completion 71 Ph.D. and 80 master’s students. He holds 69 U.S. patents and has published 238 journal articles and more than 596 refereed technical pa- pers. His research interests include high-frequency power conversion, renewable energy, high-density electronics packaging and integration, and modeling and control.

Dr. Lee is the recipient of the William E. Newell Power Electronics Award in 1989, the Arthur E. Fury Award for Leadership and Innovation in Advancing Power Electronic Systems Technology in 1998, and the Ernst-Blickle Award for achievement in the field of power electronics in 2005. He has served as the President of the IEEE Power Electronics So- ciety (1993–1994). He was named a Member of the National Academy of Engineering in 2011.

Qiang Li (M’11) received the B.S. and M.S. de- grees in power electronics from Zhejiang Uni- versity, Hangzhou, China, in 2003 and 2006, respectively, and the Ph.D. degree in electrical engineering from Virginia Tech, Blacksburg, VA, USA, in 2011.

He is currently an Associate Professor with the Center for Power Electronics Systems in The Bradley Department of Electrical and Computer Engineering of Virginia Tech. His research inter- ests include power management for distributed

power systems, applications of wide-bandgap (WBG) power devices, high-frequency power conversion and controls, magnetics and EMI, high- density electronics packaging and integration, and renewable energy.

Dr. Li was the recipient of the First Place Prize Paper Award for 2016 in the IEEE TRANSACTIONS ON POWER ELECTRONICS. He was also a re- cipient of the 2017 National Science Foundation (NSF) Career Award.

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