Fundamentals of Computer Architecture

NAME:_______________________ ECE 314 Final Assignment

Spring 2021

1. Consider the following pipelined processor we studied in class (registers are written in the first half of the cycle and read in the second half of the cycle and that branches are resolved during execute). Assume that initial values of all registers are Zero and memory are 5. In this part

i) Assume there is forwarding hardware. (Data forwarding is Active means instruction won’t have to wait in the decode stage for read after write (if there is any data dependency))

ii) Assumes all the branch instruction is NOT going to be taken. (Means if the prediction was wrong then you will have to flush the entire circuit and fetch new instruction accordingly)

Fill in the pipeline timing diagram at the bottom showing the execution of the DLX code given below. Use the following codes: F = fetch, D = decode, X = execute, M = memory access, W = write back, s = stall. The first instruction is filled in for you. Show only the first ten instructions executed. [List the instruction number corresponding to your pipeline diagram in the leftmost column. The numbers above each column are provided to help you count cycles.] Fill in write back cycle of each instruction:

Instr. No. Instruction Write back cycle (1) addi r1,r0,5 4 (2) add r2,r1,r3 (3) Lw r3,4(r0) (4) beq r2,r3,L1 (5) sub r7,r2,r3 (6) or r6,r2,r0 (7) L1: lw r5,12(r0) (8) beq r5,r4,L2 (9) sub r7,r3,r8 (10) add r1,r2,r7 (11) L2: xor r4,r3,r6 (12) sw r1,9(r2) (13) Sw r4,20(r1) (14) add r1,r4,r5

instruction 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 (1) F D X M W

instruction 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

2. This is the same as question 1 but now

i) Assumes there is NO FORWARDING hardware. (Means instructions will have to wait in the decode stage for read after write (if there is any data dependency))

ii) Assumes all the branch instruction is going to be taken. ( Means if the prediction was wrong then you will have to flush the entire circuit and fetch new instruction accordingly)

Fill in write back cycle of each instruction:

instruction 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 (1) F D X M W

instruction 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

3. Consider the pipelined processor below. (No data forwarding and no branch prediction)

Assume that this processor is going to run the following program:

1. add r1,r2,r3 2. lw r2,4(r4) 3. and r13,r3,r7 4. sw r3,12(r0) 5. addi r5,r3,100 6. sw r4,100(r6)

What will be the control signal at cycle number 5. Give the values of control signals A to D in this cycle:

A:_____ B:_____ C:_____ D:_____

List what instructions will be in each stage in cycle 6

Fetch:___________

Decode:___________

4. Indicate whether a data dependency stall is needed when executing the following pair of assembly instructions on a pipelined processor:

Data dependency stall needed? (yes or no)

Data dependency stall needed? (yes or no)

beq r1,r3,L1

and r2,r1,r6

add r2,r4,r5

and r4,r3,r6

beq r3,r2,L1

B

A D C

Execute:___________

Memory:___________

Writeback:___________

add r1,r3,r5

sub r4,r1,r5

beq r1,r3,L1

and r2,r4,r6

sw r3,10(r6)

addi r5,r3,20

and r7,r2,r6

lw r4,20(r7)