My homework related with sequential circuits in electronics.

Sequential circuits The defining characteristic of a sequential circuit is the presence of internal state. The state can change over time, based on the inputs to the circuit, and influence the outputs of the circuit. The output of the circuit is a function of not only the current input, but also its history. Sequential circuits can be categorized into ​synchronous​ and ​asynchronous​. Synchronous circuits employ periodic clock signals, which drive the global and synchronized changes of state, while asynchronous circuits are not clocked and their state changes at arbitrary points in time, such as when a result is ready. Even though asynchronous circuits have various desirable properties, such as reduced power consumption due to the lack of chip-wide clock networks, potentially better performance and reduced dependence on the specifics of the underlying physical technology, they are practically nonexistent in the wild. The reason for this might be primarily historical, but other factors include the lack of tooling and resources for asynchronous circuit design and the difficulty in their testing and debugging. In the following we will deal with synchronous designs only. Note that this is still an abstraction. Underneath which the inherently asynchronous physical layer exists and sometimes shows through, such as when designing reset circuits, using multiple clock signals or just interacting with the outside world.

State storage The most basic circuits which are able to keep state are latches. Latches are asynchronous and level-sensitive, their state changes when their inputs are asserted and the value is propagated to the output instantly. Latches are to be avoided in modern designs. Synthesis tools will often let you create a latch in your circuit, but this is almost never desirable. When the synthesizer warns you that a latch was inferred, treat this as an error! Synchronous elements which keep state are called ​flip-flops​. Flip-flops come in many varieties and configurations (RS, JK, T, etc.) The only relevant type in practice is the D flip-flop, which acts as a simple single bit memory element and does not need any fancy excitation logic to be built around it in a circuit. The operation is simple - at the active clock edge, the input state (D) is captured and presented on the output (Q), the output is stable until the next clock edge. The active clock edge is most often the rising edge, when the clock signal goes from low to high level.

Only the input D, output Q, and the clock input conventionally marked by a triangle, will be present on every flip-flop. Other common ports include, but are not limited to:

● Enable input (ENA, EN) - the output keeps state unless ENA is asserted ● Set, reset - sets the output to 1 or 0 on the next active clock edge ● Asynchronous set, reset - set the output to 1 or 0 immediately ● Complementary output !Q, the negation of Q

Asynchronous set and reset usually have higher priority than their synchronous counterparts, set and reset inputs usually have higher priority than the enable input. Flip-flops transfer their input to the output in the following cycle -- the signal is delayed by one cycle:

Setup and hold time For the proper functionality of a flip-flop, some constraints on the input signal must be observed. There is a window around the sampling clock edge, during which the input signal must not change. If the signal changes during this window, the proper functionality of the flip-flop is not guaranteed and can lead to serious failures which can propagate through the circuit. The captured input might belong to a different clock cycle and the consistency of the whole circuit won’t be preserved. The flip-flop can also linger in a metastable state for an unknown amount of time, during which the output level lies between the usual logical levels and the circuit can enter states not unlike those induced by undefined behavior in the C language - complementary outputs might take on the same value, downstream circuit might obtain different values from the same outputs. Therefore, ​it is essential to ensure that timing constraints are met​ to ensure proper functionality of a circuit. From the system point of view, it is only necessary to analyze paths from flip-flop outputs through combinatorial logic to flip-flop inputs during a single clock cycle to ensure that all timing requirements are satisfied. The design is partitioned by flip-flops into disjoint segments, which do not influence the timing of the other segments and only local analysis is necessary to show that the circuit will meet the requirements globally.

The amount of time for which the flip-flop input must not change before the active clock edge is called the setup time, the amount after the clock edge is called the hold time. For the following analysis, the following quantities will be used:

● T​setup​ - setup time ● T​hold​ - hold time ● T​clk-to-Q​ - delay between the active clock edge and the update of flip-flop output ● T​clk​ - length of a single clock period, time between two active clock edges ● T​prop​ - propagation delay between flip-flop input and output, including delays in routing

resources and in combinatorial logic

From the point of view of the flip-flop - the window during which D must be stable is located around the active clock edge.

From the system point of view, the hold time is to be analyzed with respect to the current clock edge, but the setup time causes issues at the next edge, as the signal propagates from one flip-flop to another:

The clock of the source and destination flip-flop might not be identical and might be skewed.

Setup time The signal at the flip-flop input must be stable before the clock edge for at least the required setup time. For the

T​setup​ + T​prop​ + T​clk-to-Q​ T​clk≤ Conversely, setup slack calculated as T​clk​ - (T​setup​ + T​prop​ + T​clk-to-Q​) and must be larger than zero for the design to operate properly. Setup time violations are common and usually indicate that the propagation delay through the circuit or the clock frequency is too high. Reducing the clock frequency helps, but usually the better solution is to restructure the circuit and reduce the delay through the combinatorial logic between flip-flops by restructuring it and reducing the amount of work to be done in a single clock cycle. Setup time violations also appear when there are problems with clocking circuitry, so it is recommended to consult the full output of the timing analyzer to see where the failing paths lie.

Hold time The hold time requirement specifies the minimal amount of time, during which the input must not change after the active clock edge. For the circuit to work properly, the following must hold:

T​hold​ T​clk-to-Q​ + T​prop≤ The derived hold slack, calculated as T​clk-to-Q​ + T​prop​ - T​hold​, indicates the reserve, by which the propagation delay could be shortened and must be larger than zero. Hold time requirement violations are not common and usually point to other issues in the design, such as poorly designed clock network or simply indicate that the clock connected to the flip-flop is not the right one and that the data input does not change synchronously to the flip-flop clock. Connecting the flip-flop Q directly to D is usually possible. Note that the hold time requirement does not depend on the clock frequency, as it relates to only a single clock edge. Timing analyzers commonly report ​worst negative slack​ (the minimal negative calculated slack), and ​total negative slack​ (sum of all calculated negative slacks) as a summary indicator of timing violations. A ​slightly ​broken circuit will often still work and might be good enough for

testing purposes. The particular properties vary with manufacturing process, temperature and voltage and the analysis is carried out for multiple points in this space, so if the actual conditions are not extreme, there is often ample reserve in the abilities of the circuit. On the other hand, never ship a design which fails timing analysis! Note that a practical calculation must also deal with clock skew - the clock edge might not reach the launch and capture flip-flops at the same point in time. When the clock edge arrives at the capture flip-flop delayed relative to the launch flip-flop, it is beneficial to the setup time slack, but also it reduces hold time slack at the same time. Careful layout of the physical circuit might help timing closure and trade off hold slack for setup slack and vice versa.

Example sequential circuits In the following is a small assortment of simple but common sequential circuits. The circuits assume that the flip-flop state is initialized to zero. On a contemporary FPGA, this is a valid assumption and flip-flops can be initialized to any value. Note that this is not the case in ASIC design or even when using discrete flip-flop ICs. In these cases, properly resetting the circuits is necessary. We will deal with resets later. Perhaps the simplest sequential circuit is the edge detector. The following circuit has 3 outputs, which report whether a rising, falling or any type of edge has been encountered in the incoming signal.

Another simple but common circuit is the shift register. Pictured is a 4-bit shift register with serial input and parallel output. In every clock cycle, the values move by one place in the register chain. Shift registers are commonly encountered in input and output circuits, where they are used to serialize and deserialize data or in delay lines inside circuits when it is necessary to delay some signals so that they arrive at their destination in the appropriate cycle.

The following circuit calculates the simple 4-point moving average (assuming that 2 low bits of the result are treated as the fractional part).

A simple pulse width modulator with a 3-bit counter. The WIDTH input specifies for how many cycles should be the output active during the counter period. Useful for driving LEDs or motors for changing the brightness and torque respectively.

Pulse generator with synchronous reset. The following circuit generates a pulse every 8 clock cycles, the reset input realigns the output pulse position.

State machines Automata theory provides a powerful framework for design of sequential circuits. Formal models for finite automata with output include the Moore and Mealy machines, but the standard mathematical foundation for finite state machines still apply. Moore and Mealy machines differ only slightly: Moore machine’s output is derived only from the current state, while a Mealy machine can also use the input data to generate the output. The model of a state machine consists of three blocks:

The next state logic is purely combinatorial. Based on the state machine input and the current state, it identifies which state shall the machine transition into. This block implements the transition function of the automaton. The state is stored in the next block, which should consist purely of memory elements. The output logic generates the output vector based on the state and, in the case of Mealy machines, also based on the input vector. Choosing a particular state encoding has a very strong influence on the complexity and performance of the state machine. The most efficient encoding in terms of flip-flops used will encode the states as binary numbers, but this might complicate output and next state logic. A

common choice for high maximum frequency is the one-hot encoding, which uses one flip-flop per state, only one of them is active at a time. This simplifies the next state generation, as only a single bit needs to be set. Another good choice is to encode states in a way such that the output logic contains only wires and no gates. Unfortunately, encoding states is a tradeoff and no optimal way exists except for checking all possible encodings.

Example state machine Design a machine, with 4 buttons: Button 1, Button 2, Button 3 and Reset, the buttons generate a single cycle pulse when pressed, and two outputs, Unlocked and Alarm. The user presses the buttons in sequence. When the buttons are pressed in the sequence 1, 2, 3, the Unlocked output shall turn on. When the user makes a mistake, the machine should enter an error state and the Alarm output shall turn on. Pressing the Reset button returns the machine to the initial state. Note that the specification is vague and many details are not obvious, such as what should happen when multiple buttons are pressed at the same time or how exactly the Reset button should behave in various states. Determining what exactly needs to happen is the job of the designer - you. The next step is to identify the states the automaton will have and the transitions between them. It is often useful to draw a state diagram during this phase. The machine outputs do not depend on the state of the inputs, so the machine will be of the Moore kind, because the output does not depend on the input directly. If the output should have been dependent on the inputs, the tables in the output column would need to contain another level, which would describe the outputs based on the possible input states. A Mealy machine can be expressed as a Moore machine wrapped in combinatorial glue logic, so the effort rarely seems to be worth the trouble. The following step is to derive the transition table and encode the states:

State Next state Output State encoding

initial

00001

1 digit 00010

Press 1 1 digit

Press 2 or 3 error

Otherwise initial

Unlocked 0

Alarm 0

Press 2 2 digits

Press 1 or 3 error

Unlocked 0

Alarm 0

The one-hot encoding ensures that the output logic is trivial - bit 1 is the Unlocked output, bit 0 is the Alarm output. For state storage, 5 flip-flops are necessary and should be initialized to 10000. The complex part is the next state generation logic, which will have 4 inputs for the external inputs and 5 inputs representing the current state and 5 outputs representing the next state. From the state, excitation equations for the flip-flops can be derived. Note that the transition function and the equations do not need to be total, because the buttons are pressed in sequence and the encoding is one-hot.

)D0 = RST Q⋁ ( 0 ⋀ B1 ⋀ B2 ⋀ B3 ⋀ RST )D1 = (Q ) Q0 ⋀ B1 ⋁ ( 1 ⋀ B1 ⋀ B2 ⋀ B3 ⋀ RST )D2 = (Q ) Q1 ⋀ B2 ⋁ ( 2 ⋀ B1 ⋀ B2 ⋀ B3 ⋀ RST )D3 = (Q ) Q2 ⋀ B3 ⋁ ( 3 ⋀ B1 ⋀ B2 ⋀ B3 ⋀ RST

)D4 = (Q B )) Q B )) Q B )) Q0 ⋀ ( 2 ⋁ B3 ⋁ ( 1 ⋀ ( 1 ⋁ B3 ⋁ ( 2 ⋀ ( 1 ⋁ B2 ⋁ ( 4 ⋀ B1 ⋀ B2 ⋀ B3 ⋀ RST From these, the circuit for the transfer function can be derived.

2 digits

00100

open

01000

error

10000

Press Reset initial

Otherwise 1 digit

Press 3 open

Press 1 or 2 error

Press Reset initial

Otherwise 2 digits

Unlocked 0

Alarm 0

Press Reset initial

Otherwise open

Unlocked 1

Alarm 0

Press Reset initial

Otherwise error

Unlocked 0

Alarm 1

The main lesson here is to not bother designing state machines by hand and use a HDL - laying out complex circuits by hand is not feasible unless you live in the 70’s. The finite automaton abstraction is nevertheless very powerful and the three block structure useful for a hassle-free FSA design. The best approach to designing complex designs turns out to be mixed, with some parts being better expressed as state machines and other parts designed ad-hoc. Large state machines should be often broken down into multiple smaller ones, which communicate with each other. It is also useful to design the datapath first, and then use a FSAs to create the control logic around it. Even more important than in software is the recommendation to keep the various submodules of the circuit small and simple, as you cannot cheat the fact that the physical circuit needs to be laid out.

Exercises 1. Exponential smoothing is a simple technique for low-pass filtering of numerical data,

defined as , where is the result at time , is a constant1 )sst = αdt + ( − α t−1 st t 0 < α < 1 smoothing factor and is the input value at . Design a circuit, which receives a singledt t 8-bit value per clock cycle and produces one 8-bit result per clock cycle for ..5α = 0 Draw a schematic.

2. Design a circuit, complementary to the edge detector, which induces a level change in the output signal when a pulse is seen on the input. Draw a schematic. Ensure that the

circuit works properly by checking that the output of the circuit corresponds to that of the D signal in the timing diagram for the pulse detector above shifted one cycle to the right when the input is the EDGE signal.

3. What is the maximum frequency at which is the following circuit able to operate? Where is the critical path? Assume that the flip-flops have a setup time requirement of 1.5 ns, hold time requirement of 1 ns, clock-to-Q time of 1 ns and that the propagation delay of a gate is 2 ns, routing delays negligible. Ignore paths connecting outside of the circuit.

4. Consider the simple moving average filter circuit shown above. Assume that the delay

through an adder is 5 ns, routing delay negligible and the flip-flops have setup time of 2 ns. a) What is the maximum frequency, at which is the circuit able to operate? b) The adders perform the additions unnecessarily late. Can you reorder the circuit, possibly adding more flip-flops, so that the maximum frequency increases? What is the new maximum frequency?

5. Physical switches have an undesirable property - switch bounce. When pressed, the contacts can take multiple milliseconds to mate properly and the output signal is unstable during this time, possibly generating multiple events in the downstream circuit. To debounce the signal, the following procedure can be used: create a counter, if the raw button signal is 0, reset the counter, if the raw button signal is 1, increment the counter. Stop counting and report that the button is pressed when a high enough value is reached. Assume that you have a 50 MHz clock available and that the button will settle within 5 ms. Draw a schematic.

6. The pulse width modulator has an important flaw - when the WIDTH input changes at wrong time, the output will contain glitches. Modify the circuit so that the WIDTH is stored and reloaded only when the counter overflows. Draw a schematic.

7. The lock state machine is not designed securely, even though the specified requirements are satisfied. Can you find a way of opening the lock, even though you do not know the correct sequence? What is the problem? How would you avoid it?