Abstract—Energy-efficiency is one of the most challenges of designing future heterogeneous multicore system, beyond performance, hereby we propose a performance-energy effi- ciency analytical model for integrated heterogeneous parallel multicore system which is promising to be used for big data applications. The model extends the traditional computing- centric model by considering the overhead of data preparation which can not be neglected in heterogenous multicore processor system any more.

The analysis clearly shows that higher parallelism gained from either computation or data preparation brings greater energy-efficiency. Improving the performance-energy efficiency of data preparation is another promising approach to affect power consumption. Therefore, more informed tradeoffs should be taken when we design a modern heterogeneous processor system within limited budget of energy(power).

Keywords-Energy-Efficiency; Overhead of Data Preparation; Dataflow Computing Model; Performance Evaluation; Hetero- geneous Multicore System.

I. INTRODUCTION

As multicore processors have become mainstream, it has thus become crucial to identify performance bounds and performance scaling properties in exploiting the massive parallelism they may offer [1]. Computer architecture has been transiting from the homogeneous multicore era into the heterogeneous era [2], which means that the memory wall[3] and communication issues will increase the gap between the performance of an ideal processor and that of apractical processor because the overhead of data preparation becomes an unavoidable key parameter.

Furthermore, energy efficiency is one of the most chal- lenging issue as large-scale increase trend of integration CMOS devices which has led to fused architectures with su- perscalar central processing units (CPUs) and light-weighted streaming processor units (e.g. graphics processing units (GPUs), FPGA accelerators and ARM cores). Multicore systems with heterogeneous processing elements are becom- ing the mainstream in the field of future processor design. Recent examples include Intel’s MIC[4], AMD’s Kabini[5], and NVIDIA’s Project Denver[6], etc. Especially, as the rapid development of manufacture process and promising technologies, it becomes probable to make heterogeneous kilo-core system by integrating the general-purpose (non-

graphics or data flow) computing units and GPGPU on a single chip in the near future.

Here, we classify the processors(cores) in heterogeneous mutlicore system as big processor and little core respectively. As the density on multicore chip increase, future heteroge- neous multicore parallel system will have to take seriously consideration on how to achieve higher performance and manage hardware/software resources while maintaining their power(energy) consumption within a limited budget. This challenge will stimulate multicore processor architect to develop new approaches that pursuit better performance per watt rather than simply yielding higher performance.

In this paper we model computer system, from the view of data flow computing model, by extending the fraction of data preparation rather than the state-of-art Amdahl’s law on basis of computing-centric system which never takes into account potential cost of data preparation. Our contributions are mainly (1) Extending the performance model by considering the overhead of data preparation, and then making new equations to evaluate performance of heterogeneous parallel multicore system; (2) Building a performance-energy effi- ciency model and evaluating heterogeneous parallel multi- core system; (3) Comparing the results to that of traditional Amdahl’s law.

This paper is organized as follows. Section II presents some related works. Section III presents a performance model of integrated heterogeneous multicore system by considering the overhead of data preparation after revisiting traditional Amdahl’s law. Section IV proposes performance- energy efficiency model for heterogeneous multicore system and creates a new equation of describing performance- energy ratio by referring to some basic variables from [7, 20]. Section V evaluates the performance-energy of heterogeneous multicore system by comparing to the results of traditional Amdahl’s law. Section VI concludes our work and future missions.

II. RELATED WORK

There are a lot of research achievements in theory to harness power(energy) consumption[7–12]. Woo and Lee[7] extend Amahl’s law for energy-efficient computing of many- core, who classified many-core design styles as three type:

symmetric superscalar processor tagged with P∗, symmetric smaller power-efficient core tagged with c∗, and asymmetric many-core processor with superscalar processor and many smaller cores tagged with P + c∗. The research results show that heterogeneous architecture is better than symmet- ric system to save power. Similarly, Marowka[8] extends Amdahl’s law for heterogenous computing, and investigated how energy efficiency and scalability are affected by the power constraints for three kind of heterogeneous com- puter system, i.e., symmetric, asymmetric and simultane- ous asymmetric. The analysis shows clearly that greater parallelism is the most important factor affecting power consumption[8]. Karanikolaou, et al evaluate experimental energy consumption based on distributed and many-core platforms. They evaluated for the power their processors demand at the idle and fully utilized state. In proportion to the parallelized percentage each time, the estimations of the theoretical model were compared to the experimental results achieved on the basis of the performance/power and performance/energy ratio metrics[9]. Kim et al focus on the energy efficiency of the sequential part acceleration, and how to determine the optimal frequency boosting ratio which maximize energy efficiency. According to the results, energy efficiency of the acceleration increases with the number of cores and an optimal frequency boosting ratio can be determined. Accelerating the sequential part of a program is a promising approach to improve overall performance in parallel processors[10]. London̄o et al present a study about the potential dynamic energy improvement that can be achieved when hardware parallelization is used to increase the energy efficiency of the system rather than to increase performance. They model the potential dynamic energy improvement, optimal frequency and voltage allocation of a multicore system in terms of extending Amdahl’s law[11]. Ge et al propose a power-aware speedup model to predict the scaled execution time of power-aware clusters by isolating the performance effects of changing processor frequencies and the number of nodes. By decomposing the workload with DOP and ON-/OFF-chip characteristics, this model takes into account the effects of both parallelism and power aware techniques on speedup[12].

In field of practical products or implementations, low power techniques and algorithms for multicore system, such as dynamic voltage/frenquency scaling(DVFS) and heterogeneous microarchitectures, are recommend to reduce power(energy) by lowering the voltage and frequency or by migrating execution to a more efficient, but smaller size of chip[13–18]. Sawalha and Barnes demonstrate that significant reduction in energy consumption can be achieved by dynamically adjusting mapping as application behav- ior changes with new program phases. Significant ener- gy reduction over random scheduling of programs within a heterogeneous multicore processor[13]. Nowak employs the Convey HC-1, a heterogeneous system equipped with

four user-programmable FPGAs, for our investigations to- ward energy-efficient computing. He find that heterogeneous systems based on reconfigurable hardware, efficient data exchange mechanisms, data-driven and component-based programming, and task-parallel execution can help achieve power-efficient exascale systems in future[14]. Lukefahr et al developed an offline analysis tool to study the potential energy efficiency of fine-grained DVFS and heterogeneous microarchitectures, as well as a hybrid approach[16]. Our prior work on designing a fused cache with compacted cache directories and a framework of accessing unified memory address space of heterogeneous parallel multicore system[15, 17]. Wang and Ren coordinate inter-processor work distribution and per-processor’s frequency scaling to minimize energy consumption under a given scheduling length constraint. Through several evaluations on a real CPU-GPU system, our results gain 14% energy reduction compared with static mapping strategy[18].

III. PERFORMANCE MODEL OF INTEGRATED HETEROGENEOUS MULTICORE SYSTEM

Four decades ago, Gene Amdhal mainly focused on performance of computer for a special case of using mul- tiple processors in parallel when he argued for the single- processor approach’s validity for achieving large-scale com- puting capabilities[19].

Here, we are more interested in the power-efficiency or energy-efficiency of future integrated heterogeneous multi- core processor system. Hence, we develop analytical power models of integrated heterogeneous multicore and formulate metrics to evaluate energy-efficiency on the basis of perfor- mance with considering the overhead of data preparation.

A. Revisit Amdahl’s Law

According to Amdahl’s law, the formula for computing the theoretical maximum speedup(or performance) achiev- able through parallelization is as follows:

SA(fc,c) = 1

1 −fc + fcc (1)

where c is the number of cores or processors, and fc is the fraction of computation that programmers can parallelize(0 ≤ fc ≤ 1)[20].

The equation is correct if three potential key assumptions are verified: (1) the programs to be executed are of fixed- size, and the fraction of the programs that is parallelizable remains constant as well; (2) there exists an infinite memory capable of meeting the requirements as the number of cores increases; and (3) the overhead of preparing data to be used by computing units, such as accessing memory, communication on-chips or off-chips and synchronization among cores, can be completely neglected.

Because of the “memory wall,” the overhead of data preparation including memory access, transmitting data on-

1-fc fc/c 1-fh kc(1-α) fh

1-fc fc 1-fh (1-α) fh α fh

cores

core

(1-kc)(1-α) fh α fh

Pc 1-Pc

Figure 1. Normalized task (equivalence time). Split between Computation and Data Preparation.

and off- chip, transferring data between CPU memory s- paces and GPU memory spaces for heterogeneous system, synchronizing processes, etc., becomes so significant that it cannot be ignored any longer. However, Amdahl’s law only considers the cost of computation to the exclusion of the cost of preparing data for computation, especially when modeling a heterogeneous multicore system. Therefore, we will take consideration of the overhead of data preparation in heterogeneous multicore system.

B. Analytic Model of Integrated Heterogeneous Multicore System with Considering the Overhead of Data Preparation

We will thus now assume that the whole cost of executing a program can be split into two independent parts, from the view of data flow computing model, one of preparing data for execution and the other one of running instructions when the required data are ready. Therefore, the Overhead of Data Preparation (ODP) includes the whole cost of preparing data for execution, to the exclusion of actual execution. As shown in Figure 1, ODP can be considered to produce a new speedup equation by extending legacy Amdahl’s Law. We will call it the “Extended Amdahl’s law” as expressed in equation (2).

SEA(fc,c,pc) = 1

((1 −fc) + fcc )pc + (1 −pc) (2)

where pc denotes the fraction of computation, 1−pc denotes the fraction of Data Preparation normalized to computation portion: since the clock frequencies and the ISAs of CPUs, GPUs, off-chip bus and memory arbitrator would likely be different, we should use the performance of Data Preparation instructions equivalent to that of computing instructions. Therefore, the legacy Amdahl’s law is a special case of the ”Extended Amdahl’s law” where pc = 1. The fc is the parallelizable computation portion, 1 −fc is the sequential computation portion.

As shown in Figure 1, however, equation (2) does not make allowances for the introduction of techniques that would decrease or eliminate the overhead of data prepara- tion. We further divide the portion of data preparation into three sub-parts: 1 − fh, αfh and (1 − α)fh. fh denotes the portion of the program that can be overlapped with “computing” instructions in theory, where 0 ≤ fh ≤ 1.

Furthermore, we introduce a variable dc to model how much percentage of data preparation that cannot be over-

lapped on a c cores system even adopting advanced tech- nologies, where 0≤ dc ≤ 1. After normalization to the computation, the fraction of data preparation instructions which cannot be overlapped on a c core system becomes fud = (1−fh) +dc ·(1−α)fh. On the opposite, the fraction of data preparation instructions which can be overlapped on a c core system becomes fpd = αfh + (1−dc) ·(1−α)fh, where fud+fpd = 1. While, the 1−fh denotes the fraction of data preparation which is closely dependent on computation.

Therefore, we can extend Amdahl’s law to be a new equation called “Enhanced Amdahl’s law”. The performance speedup is governed by:

S ′

EA(fc,c,pc,fud) = 1

((1−fc)+ fcc )pc +fud(1−pc) (3)

IV. PERFORMANCE-ENERGY EFFICIENCY MODEL OF INTEGRATED HETEROGENEOUS MULTICORE SYSTEM

A. Performance Model of the Integrated Heterogeneous Multicore System

Similar to the assumption in [4], we assume that the integrated heterogeneous parallel multicore system is built with one big processor which consists of r BCEs, and c little cores which consists of only one BCEs for each core. The sequential computation and sequential data preparation are only executed by the big processor, and the parallel computation and parallel data preparation are also only executed by c little cores. Besides, the big processor would be idle while the little cores are executing the parallel instructions[7].

Executing the sequential fraction of a given program (includes the cost of executing sequential computing instruc- tions and the cost of sequential fraction of data preparation) at only one big processor with r cores takes (1−fc)·pc+fud· (1 −pc), whereas executing the parallel fraction of a given program simultaneously at c little cores which takes fc

c·sc ·pc.

sc represents the performance of a little core normalized to that of a big processor, where 0 ≤ sc ≤ 1. Therefore, the performance speedup for integrated heterogeneous parallel multicore system while considering the overhead of data preparation is governed by:

SHSEA (fc,c,pc,fud) = 1

((1−fc)+ fcc·sc )pc +fud(1−pc) (4)

B. Performance-Energy Efficiency Model

We also adopt the variables sc, wc, k and kc from [7], where sc represents a little core’s performance normalized to that of a big processor (0 ≤ sc ≤ 1), wc represents an active little core’s power consumption relative to that of an active big processor (0 ≤ wc ≤ 1), k represents the fraction of power that the big processor consumes in idle state (0 ≤ k ≤ 1), and kc represents the fraction of an little core’s idle power normalized to the same core’s overall power consumption (0 ≤ kc ≤ 1). Assumed that the big processor in active

state consumes a power of 1. During the sequential fraction of executing a given program, the amount of power that the big processor consumes is 1, and the amount of power that c little cores at idle state consume c·wc·kc. During the parallel fraction of executing a given program, the big processor consumes k, and the c little cores consume c ·wc. Because the cost(performance) of executing sequential and parallel portion are respectively pws = (1−fc) ·pc + fud · (1 −pc) and pwp =

fc c·sc ·pc + fpd · (1 −pc), the average power is

W = pws · {1 + c ·wc ·kc} + pwp · {k + c ·wc}

((1−fc)+ fcc·sc )pc +fud(1−pc) (5)

We can also model, similar to [7], the perfor- mance(speedup) per watt(S/W) equation which represents the performance achievable at an average power(W) in Equation 6.

S W

= 1 ((1−fc)+ fcc·sc )pc+fud(1−pc)

× ((1−fc)+ fcc·sc )pc+fud(1−pc)

pws·{1+c·wc·kc}+pwp·{k+c·wc}

= 1 pws·{1+c·wc·kc}+pwp·{k+c·wc}

(6)

V. EVALUATION AND ANALYSIS Assumed that the integrated heterogeneous multicore sys-

tem consists of one big processor(e.g. superscalar multicore CPU processor) and c little cores(e.g. GPU cores). In order to compare the results of S/W with that in [7], we also set sc, wc, k and kc as 0.5, 0.25, 0.3 and 0.2 respectively. we set the variables pc, fh, α, and dc as 0.6, 0.8, 0.699 and 0.333 respectively.

Figure 2 shows the analytical results of performance for asymmetric multicore system. Figure 2(a) shows that the maximum relative performance of P + c∗ is 56.39, where f = 0.99 and c = 256. As shown 5 curves in Figure 2(a), the relative performance dramatically increases as the number of little cores increase when f = 0.99. It means that a little bit more percentage of parallel computation would bring huge performance gain. For example, the curve of f = 0.99 and f = 0.9, only 10% increase on parallel computation gets more than 5 times increase of performance where c = 256. However, the performance increase of each curve in Figure 2(b) is much more gently than that in Figure 2(a), and the maximum of relative performance is just only 3.35 where f = 0.99 and c = 256. The reason is that much more cost would be consumed by data preparation, and the increase of relative performance is the result of balancing computation and data preparation. The Figure 2(b) also shows that a program with low percentage of parallel computation, such as f = 0.3, can not get great relative performance increase even continuously increasing the number of little cores up to 256. Unfortunately, even though the percentage of parallel computation is higher than 90%, it can not get dramatic increase as that in Figure 2(a).

As shown in the Figure 3(a) and Figure 3(b), for each kind number of little cores, higher fraction of parallelizable

(a) Woo’s state-of-art asymmetric multicore system P + c∗.

(b) Integrated heterogeneous parallel multicore system with consider- ing ODP where pc = 0.6, fh = 0.8, α = 0.699, and dc = 0.333.

Figure 2. Scalable Performance Distribution of Heterogeneous Asymmet- ric Multicore(HAM) where sc = 0.5,wc = 0.25,k = 0.3, and kc = 0.2.

computation in a given program gets higher relative perfor- mance per watt. For example, as shown in the Figure 3(b), the values of relative performance per watt are respectively 0.5397, 0.5877, 0.6452, 0.7517 and 0.7517 where f = 0.3, f = 0.5, f = 0.7, f = 0.9 and f = 0.99 in the case of c = 16. It means that a program consisting of higher fraction of parallel execution consumes more energy. We can easily observe that the trend of curves in the Figure 3(a) are also similar to that in the Figure 3(b). The overall situation of state-of-art asymmetric multicore system is identical to that of integrated heterogeneous parallel multicore system.

In Figure 3(a), the values of relative performance per watt decrease after c = 4 (f = 0.9 and f = 0.99) or c = 8 (f = 0.3, f = 0.5, and f = 0.7). It means that as the number of little cores increase after the critical value of c, on average, the performance would become worse and worse within a fixed budget of energy. The reason is as the number of little cores increases for a fixed fraction of paral- lelizable computation in a given program, the performance of little cores will saturate. Therefore, the performance per watt decrease after the critical value of little cores. More little cores would consume more energy to maintain the

(a) Woo’s state-of-art asymmetric multicore system P + c∗.

(b) Integrated heterogeneous parallel multicore system with consider- ing ODP where pc = 0.6, fh = 0.8, α = 0.699, and dc = 0.333.

Figure 3. Scalable Performance per Watt Distribution of Heterogeneous Asymmetric Multicore(HAM) where sc = 0.5,wc = 0.25,k = 0.3, and kc = 0.2.

synchronization, communication, cache coherence, etc rather than improve performance.

However, if a program with higher fraction of computing parallelism, the slop of performance decrease becomes less slowly. For example, the curve corresponding to f = 0.99 is over the curve corresponding to f = 0.9. The reason is that higher fraction of parallel computation will have enough computing tasks to be executed on more little cores in parallel.

There is a special case in the Figure 3(b), the value of per- formance per watt is 1 where f = 0.3 and c = 1. Here, it’s the heterogeneous multicore system built with only one big processor and only one little core. The value of performance per watt discloses that the sequential cost of computation and data preparation consumes the same amount of energy to that of parallel computation and data preparation. The interesting thing is that the point is f = 0.3 which means the energy of executing 30% parallel computation in a given program is approximately identical to the energy of implementing 70%

data preparation. Comparing Figure 3(a) with Figure 3(b), we observe that

the five curves in the Figure 3(b) are more identical than that in the Figure 3(a), and they are approximate to the point around 0.1. Because some parts of sequential data preparation are executed by the big processor, and some parts of parallelizable data preparation are executed by little cores, whether the fraction of parallel computation is high or not, which can make a stable balance between sequential tasks and parallel tasks.

The maximum value of relative performance per watt for a given case (e.g. the number of little cores is 4) in Figure 3(a) and Figure 3(b) are 1.53 and 1.13 respectively. It means that the integrated heterogeneous multicore system would sacrifice 26% computing performance to implement data preparation within a fixed budget of energy, comparing to the performance in the state-of-art asymmetric multicore system based on traditional Amdahl’s law.

After considering the overhead of data preparation, the relative performance per watt will decrease much more sharply that that in the Figure 3(a) as the number of little cores increases. The reason is that the energy consumed by data preparation tasks is not taken consideration in terms of legacy performance formula of Amdahl’s law.

In practical computer system, as number of little cores increase, there would be more costs of executing data preparation, such as synchronization, communication, data transformation, etc. However, the time consumed by exe- cuting data preparation can not gain speedup performance according to traditional Amdahl’s law rather than waste energy. As a result, the Figure 3(b) highly reflects the practical relative performance per watt than that in Figure 3(a).

VI. CONCLUSION

We reevaluate the performance-energy efficiency for in- tegrated heterogeneous parallel multicore system based on the mathematical model of data flow, which splits a pro- gram(task) into computation and data preparation rather than only computation in the state-of-art Amdahl’s law. By deriving the new equation of performance-energy based on the analytic model of integrated heterogeneous multicore system with considering the overhead of data preparation, we get a new result from it and compare it with that of Woo’s work.

The results show that our model is much more closely reflecting practical heterogeneous multicore system than that in traditional Amdhahl’s model. According to the results, more little cores would not bring significant performance gain after passing the critical point (e.g. c = 4 or c = 8) other than consuming more energy. Therefore, as for the heterogeneous multicore system built with one big core and many little cores, which has limited budget of energy to execute a program(task). Its gain of performance per watt is

increased by improving the fraction of parallel task including parallel computation and parallel data preparation, rather than by increasing the number of little cores. Generally, the fraction of parallel computation in a given program is hard to be improved by instructions level parallelism (ILP), threads level parallelism (TLP) nowadays. Howev- er, I have another approach to accelerate performance by improving the fraction of parallel data preparation, such as data prefetching, no-copy data transfer, solid-state storage, computing on memory and other emerging technologies.

We will keep on investigating the performance gain within limited energy(or power) budget for supercomputer or clus- ter built with multiple big processors and many little cores while considering the overhead of data preparation.

ACKNOWLEDGMENT

We thank the anonymous reviewers for their invaluable comments. This work was partially funded by the Shang- hai Municipal Natural Science Foundation under Grant No.15ZR1428600 and the National Science Foundation of United States under Grant No.CCF-1065448.

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