2 pages report on paper [Doyle91] B. Doyle, B. Fishbein, and K. Mistry, "NBTI-enhanced hot carrier damage in p-channel MOSFETs," Proc. Intl. Electron Devices Meeting, 1991, pp. 529-532A.

NBTI-Enhanced Hot Carrier Damage in p-Channel MOSFET's

Brian S. Doyle, Bruce J . Fishbein and Kaizad R . Mistry

Digital Equipment Corporation 77 Reed Road, Hudson, MA 01749

ABSTRACT

The behavior o f p-MOS devices at elevated temperatures has been studied w i t h respect t o hot carrier stress. It is found that that the hot carrier stress damage a t V,=Va INCREASES as temperature increases, contrary t o conventional hot carrier behaviour. The cause o f the damage is identified as being negative bias temperature instability (NBTI)-related. which is greatly accelerated under hot carrier stress conditions. A com- parison of the a.c. hot carrier lifetimes at T=25 and 125 "C show t h a t the damage behaviour is quite different, the low temperature stress resulting i n an increase i n drive current, while the NBTI-dominated high temperature stress shows a decrease in drive current. It is concluded that this can be the major source o f hot carrier damage at elevated temperatures ( 2 100 "C) i n the a.c. stressing o f p-MOS transistors.

INTRODUCTION O f the many reliability issues arising from the use and the

integration o f circuits using Silicon CMOS transistors, one o f the earliest identified was Negative Bias Temperature Instabil- ity (NBTI) [1-3].The phenomenon arises at high temperatures (usually above 100 "C) under the influence o f large negative voltages on the gate o f n- and p-channel transistors. The effect seen is a shift i n the threshold o f the transistor t o more neg- ative gate voltages, and a decrease i n the subthreshold slope due t o an increase in the amount o f positive charge i n the ox- ide, as well as an increase i n interface state densities 11.21. Another field of reliability is the hot carrier effect. where the application o f high voltages t o the drain o f a transistor ( w i t h the gate voltage above Vt) causes a gradual change i n the I- V characteristics. Both interface states and oxide traps are created during hot carrier stress of p-MOS transistors [4-61.

While much is known about the effect o f gate voltage stress on the device characteristics, l i t t l e is known o f the interaction of NBTI w i t h hot carriers. This paper studies the importance o f the N B T l effect under conditions o f hot carrier injection.

NEGATIVE BIAS TEMPERATURE INSTABILITY

One of the most important differences between N B T l and

Vd stress c, -1.5

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0 4

- 2 . 5

-3.0 1 . 8 2 . 1 2 . 4 2.7 3 . 0

\ -3.0 :-2*5L. 1 . 8 2 . 1 2 . 4 2.7 3 . 0

1000/T

Figure 1: Amount of drain current degradation as a function of 1000/T for gate voltage N B T l stresses (Vd=O V). and for Hot carrier stress at Vd=Vp.

other reliability concerns is that it occurs under conditions i n which there is no measurable charge transport. I n many reli- ability fields, current flows. which directly or indirectly causes damage (such as ESD. Hot Carrier Effects. Electromigration. T D D B ) . I n the case o f NBTI. it suffices that a small electric field be applied t o the gate oxide (of the order o f 1-2 MV/cm) t o cause a very substantial degradation of the the transistor char- acteristics. Comparing this mechanism w i t h Fowler-Nordheim degradation, which it resembles most (as in b o t h cases, a volt- age is applied t o the gate alone), the current passing through the oxide t o obtain an equivalent degradation on the same time scale, is of the order of I E I O times smaller for NBTI.

This degradation arises from the presence of trapped holes i n the oxide. coupled w i t h the creation of interface states [1.2]. Slow or relaxable states are also created [3]. To illustrate the effect, a set of devices was stressed (at Vg=-7.5 volts) for a fixed period of time (1200 sec) a t different temperatures (125, 150. 175. and 200°C). The drive current ( I d at vg=vd=3.3 v) was measured before and after the stress. The results o f the fixed duration measurements are shown i n Figure 1. performed on 12.5/1 p m p-channel devices w i t h an oxide thickness of 150 A and w i t h conventional junctions. Figure 1 shows the I d shift versus 1000/T. giving an activation energy of 0.35 eV. i n agreement w i t h the literature. The Vt shifts were found t o be negative, which correspond t o a net positive charge build-up at the Si-SiOz interface, also i n agreement w i t h the literature.

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HOT CARRIER STRESS It has been shown t h a t the hot carrier degradation o f p-

MOS devices at low gate voltages and a t room temperature is intimately linked t o gate current [4-61 , and that this gives rise t o an increase in transconductance. Figure 2 a) shows the amount o f transconductance change (dg,) as a function o f gate voltage, for a series o f devices stressed at Vd=-6.5 V. for 1000 seconds at 25' C. It can be seen t h a t the g, change is always positive (i.e. the transconductance increases). and t h a t it peaks at low gate voltages, around V,=0.75 V. At no point in this particular technology is the gm change negative. Figure 2 b) shows a series o f stresses performed under the same voltage conditions, b u t a t 125'C (these stress are t o be called H(TDG) stresses - High Temperature, High Drain. High Gate stresses). The time o f stress was fixed so t h a t the same degradation is obtained at Vg=-1.25 V for b o t h sets o f stresses. At low gate voltages, the low T and high T stresses appear similar. However, a t high gate voltages, the high temperature stress results in a decrease in transconductance. The decrease in transconductance indicates that a different type o f damage creation is taking place, which could be either interface donor states or positive trapped charge, b u t not negative trapped charge, as this would give an increase i n 9,.

Figure 3 shows the evolution o f the damage as a function o f time at T= 125'C. Here. stress data a t Vd=-6.0 V. Vg=-1.2 V is plotted as a function o f time, demonstrating the satura- tion effect found normally during low gate voltage hot carrier stress. Figure 3 also shows the type o f behaviour seen at vd=- 6.0 V. V,=-3.0 V. It can be seen t h a t there is a turn-around effect here, w i t h the degradation at short times resulting in an increase of the transconductance. while at longer times. the g, decreases. The initial increase is due the channel shortening effect discussed earlier, while the decrease is due t o an N B T l compensating mechanism, which degrades the transistor char- acteristics and eventually dominates at long times. A t Vg=- 5.0 V. the behaviour seen is purely transconductance degrada- tion associated w i t h NBTI-like effects. Furthermore, while low

0. 2.-

5 -0 . 2.-

-0.21 1 - 6 -5 -4 -3 -2 -1 0

Vg ( s t r e s s )

F i g u r e 2 : Transconductance change versus gate voltage of stress for a) devices stressed at 25' C. b) For devices stressed at 125' C.

vg=-1.2 v oooooooooooOOOOOCOObOOOOOOOOO

> YV v v v v v v v v v v v Vg=-3.0 _. - V ___ o.ov- vg=-5.0 o- v "%

0 0 0-

0 1 2 3 4 5

log time F i g u r e 3: Transconductance change versus time for devices stressed at different gate voltages at T= 125' C.

temperature hot carrier stress effects are limited t o changes in transconductance and drive current, in the case o f these H ( T D G ) stresses, there is also a threshold voltage change. The reason for this will be discussed below.

DAMAGE IDENTIFICATION In order t o understand the types o f damage arising at high

gate voltages, measurements following stress were perform'ed as a function o f drain bias, which was varied f r o m -0.05 V t o -2.0 V. Figure 4 shows the g, change after a stress of 150 seconds at vd=-7. Vg=-l V and T= 25' C (this stress and all room temperature stresses under low gate-high drain con- ditions will henceforth be called CHE -Channel Hot Electron). It can be seen that by vd=-l.o V. the damage created during stress no longer affects the transistor characteristics because of the localization of the damage.

Figure 4 also shows the results o f a 500 second stress at vg=vd=-6.5 V. at T= 125' C (these are the conditions that will be used throughout unless otherwise stated). This figure shows that the H(TDG) damage is very much less localized than the low temperature CHE (Figure 4 a)). Up t o vd=-l.o V. the dg, decreases t o half the amount at Vd=-0.05 V. Above -1.0 V and up t o vd=-3.3 V (the highest voltages measured) the amount o f degradation remains constant. Since b o t h the drain and the gate are biased negatively, it might be thought that the localized nature o f the damage could be the result o f simultaneous h o t carriers and N B T l (near the source end). However, seperate N B T l measurements showed the damage due t o the gate voltage alone t o be much smaller t h a t that seen above vd=-i.o V in figure 4.

The hot carrier - high temperature stresses then. creates damage t h a t is considerably more extensive than for CHE. so extensive, in fact, that it is amenable to the classical approach of linking log I d - v g shifts t o oxide traps and subthreshold gra- dient changes t o interface states (as witnessed by the change in V, a phenomenon not seen for the localized damage o f CHE). Figure 5 a) and b) show an example of this. In this case, the transistor has been stressed at vg=vd=-7.5 v at 125' c for 3000 seconds. From this graph, the t w o components o f stress

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HOT CARRIER STRESS It has been shown t h a t the h o t carrier degradation o f p-

MOS devices at low gate voltages and a t room temperature is intimately linked t o gate current [4-61 . and t h a t this gives rise t o an increase i n transconductance. Figure 2 a) shows the amount o f transconductance change (dg,) as a function o f gate voltage. for a series o f devices stressed a t Vd=-6.5 V. for 1000 seconds a t 25' C. It can be seen t h a t the g, change is always positive (i.e. the transconductance increases), and that it peaks at low gate voltages. around Vg=0.75 V. A t no point in this particular technology is the g, change negative. Figure 2 b) shows a series o f stresses performed under the same voltage conditions. b u t at 125OC (these stress are t o be called H(TDG) stresses - High Temperature, High Drain. High Gate stresses). The time o f stress was fixed so t h a t the same degradation is obtained at Vg=-1.25 V for b o t h sets o f stresses. A t low gate voltages. the low T and high T stresses appear similar. However, at high gate voltages. the high temperature stress results in a decrease i n transconductance. The decrease in transconductance indicates t h a t a different type of damage creation is taking place. which could be either interface donor states or positive trapped charge, b u t not negative trapped charge. as this would give an increase i n gm.

Figure 3 shows the evolution of the damage as a function o f time at T= 125OC. Here. stress data a t Vd=-6.0 V. Vg=-1.2 V is plotted as a function o f time. demonstrating the satura- tion effect found normally during low gate voltage h o t carrier stress. Figure 3 also shows the type o f behaviour seen at vd=- 6.0 V. V,=-3.0 V. It can be seen t h a t there is a turn-around effect here, w i t h the degradation at short times resulting in an increase of the transconductance. while a t longer times. the gm decreases. The initial increase is due the channel shortening effect discussed earlier. while the decrease is due t o an N B T l compensating mechanism, which degrades the transistor char- acteristics and eventually dominates at long times. At V,=- 5.0 V. the behaviour seen is purely transconductance degrada- tion associated w i t h NBTI-like effects. Furthermore, while low

0 . 2 ~

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93

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F i g u r e 2: Transconductance change versus gate voltage o f stress for a) devices stressed at 25OC. b) For devices stressed a t 125' C .

0 1 2 3 4 5

log time

F i g u r e 3: Transconductance change versus t i m e for devices stressed at different gate voltages at T= 125O.C.

temperature h o t carrier stress effects are limited t o changes in transconductance and drive current, in the case o f these H ( T D G ) stresses, there is also a threshold voltage change. The reason for this will be discussed below.

DAMAGE IDENTIFICATION In order t o understand the types o f damage arising a t high

gate voltages. measurements following stress were performed as a function o f drain bias, which was varied from -0.05 V t o -2.0 V. Figure 4 shows the g, change after a stress of 150 seconds at vd=-7. Vg=-l V and T= 25O C (this stress and all room temperature stresses under low gate-high drain con- ditions will henceforth be called CHE -Channel H o t Electron). It can be seen that by vd=-l.o V. the damage created during stress no longer affects the transistor characteristics because of the localization of the damage.

Figure 4 also shows the results o f a 500 second stress at vg=vd=-6.5 v. at T= 125' C (these are the conditions that will be used throughout unless otherwise stated). This figure shows that the H ( T D G ) damage is very much less localized than the low temperature CHE (Figure 4 a)). Up t o vd=-l.o V. the dgm decreases t o half the amount at Vd=-0.05 V. Above -1.0 V and up t o vd=-3.3 V (the highest voltages measured) the amount o f degradation remains constant. Since b o t h the drain and the gate are biased negatively. it might be thought that the localized nature o f the damage could be the result o f simultaneous hot carriers and NBTl (near the source end). However, seperate N B T l measurements showed the damage due to the gate voltage alone t o be much smaller that that seen above vd=-l.o V in figure 4.

The hot carrier - high temperature stresses then, creates damage t h a t is considerably more extensive than for CHE. so extensive, in fact, t h a t it is amenable t o the classical approach of linking log Id-vg shifts t o oxide traps and subthreshold gra- dient changes t o interface states (as witnessed by the change in Vt a phenomenon n o t seen for the localized damage o f CHE). Figure 5 a) and b) show an example o f this. I n t h i s case, the transistor has been stressed at v,=vd=-7.5 v at 125' c for 3000 seconds. From this graph, the t w o components of stress

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damage can be identified - oxide hole trapping (No:) f r o m the shift in the full log Id-Vu curves, and interface states ( N , , ) f r o m the change in the sub-threshold gradient (as well as charge pumping measurements). in agreement w i t h published reports on NBTI [I-31. The recovery after the application o f positive bias t o the gate (7.5 V. 3000 seconds, Figure 5 c) is also in agreement w i t h published N B T I data. It can thus be stated that H ( T D G ) stress causes the creation o f interface states plus the non-localized trapping o f holes in the oxide along the chan- nel, a part of which can relax o u t if positive bias is applied t o the gate following stress. This is very similar t o what happens in N B T I stresses.

It has also been found t h a t N B T l and H(TDG) show the same power law time dependencies. w i t h the same approximate gradient o f 0.3. further linking the t w o types o f stress.

However. the most important piece o f evidence supporting the argument t h a t the high temperature h o t carrier stresses and the NBTI stresses are similar is the temperature depen- dence. One o f the features o f hot carrier stress is t h a t as the temperature increases, the h o t carrier degradation becomes less significant at the same given voltage conditions, due t o the interaction o f the hot carriers w i t h phonons. However, it has been shown above that N B T I shows the opposite effect. and is activated w i t h temperature. Comparing classical hot carrier degradation w i t h H(TDG). Figure 6 shows strikingly different trends between the high and low temperature stresses. T h u s H ( T D G ) and CHE show similar effects w i t h temperature .

DISCUSSION Comparing activation energies between NBTI and H ( T D G )

in figure 1. plotted on an Arrhenius plot, it can be seen t h a t H(TDG) and NBTI are b o t h activated. However, curiously. they have different activation energies, w i t h 0.35 eV for N B T I . and w 0.15 eV For H(TDG). This will be discussed later on.

Many different mechanisms have been p u t forward t o ex- plain NBTI. These include electron tunnelling f r o m S i 0 2 t o Si [7]. hole tunnelling i n t o the S i O z [SI. hole trapping i n the oxide 191. oxygen vacancy formation (IO). hole trapping on intrinsic

Low vg

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F i g u r e 4: Localization o f hot carrier damage a t low and high gate voltages. The high IVul stress shows less localized dam- age.

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v9 F i g u r e 5: Log Id-vg characteristics a) before high IVgl h o t carrier stress. b) After stress. c) after grounding the terminals for 1000 seconds.

o.09[ /I H i g h Vg 0 . 0 o l : : : : ; : ! '

280 320 360 400 440 480

Temperature (K)

F i g u r e 6: Temperature dependencies for p-MOS stresses. a) Low IV,l (gm increase). b) High IVgl (gm decrease).

V g stress

= \ - .\

V d stress

21 3.0 4.5 6.0 1.5

V d

F i g u r e 7: Comparison o f gate voltage stress ((vd=v,=o V) w i t h high gate voltage hot carrier stress at T=125 C. Hot carrier stressing can be seen t o enhance the damage by over one order o f magnitude.

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hole traps [ I l l . strained bond reactions [12] and electrochem- ical reactions 1131. The experiments performed in this memo indicate t h a t the presence o f holes at the silicon - Si02 inter- face is required. The trapping o f holes in the oxide in the case o f N B T l stress, and the voltage dependence o f the trapping i n the presence o f an inversion layer, coupled w i t h the absence o f any significant Fowler-Nordheim current, suggest t h a t the presence o f large concentrations o f holes at the interface is re- quired for the creation o f NBTl damage. As the concentration o f holes is increased, so is the amount o f N B T l damage.

Stresses at high temperatures under the conditions vg=vd cause enhanced degradation o f transistor characteristics com- pared t o field/gate voltage stresses. Figure 7 shows t h a t the acceleration factor for H ( T D G ) over N B T l at 125 " C is greater by more than an order o f magnitude. Under hot carrier stress conditions. the gate voltage dependence o f the gate current shows t w o regions. a low gate voltage region consisting o f electrons, and a high gate voltage 'region where holes are the predominant component o f the gate current. Since the gate current under H C - N B T I is o f holes, it would appear reason- able t o propose that the accelerated degradation arising f r o m the H C - N B T I stress is related t o the injection o f holes i n t o the oxide. and t h a t holes, whether in the inversion layer. or injected i n t o the oxide. are the species behind this degradation mechanism.

Using this approach, the activation energy differences (Fig- ure 1) between N B T I and H(TDG) can be explained. T w o competing mechanisms interact i n the case o f H ( T D G ) - the decrease in the hot hole population w i t h increasing temper- ature. and the increase in damage associated w i t h NBTI-like effects. The result is a behaviour t h a t is less strongly activated than pure NBTI. This is what is seen in figure 6.

The sections above have discussed the H ( T D G ) effect. un- der the stress conditions vg=vd. where vd is the supply voltage or higher. In circuit functioning, however, these conditions do not arise (or rather. are not normally allowed t o arise), and the condition Vg=Vd occurs (in inverter-type operation, which

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: -2

2 -3

H

- 4 ' : 1 0 1 2 3 4 5

log t i m e

F i g u r e 8: a.c Hot carrier stress (Period=100 kHz) at 25 "C and 125 "C. The 25 "C stress ) shows an increase in drive current, while the 125 "C stress shows that the NBTI-related degradation is dominant.

is discussed here) at around v&. It might consequently be thought that H ( T D G ) stress is irrelevant t o circuit operation.

Figure 8 shows the results o f measurements taken at 25 "C and 125 "C. under dynamic stress conditions. The max- imum voltage o f the gate and drain pulses was -6.5 V. The devices were stressed under dynamic inverter conditions, by using t w o pulse generators, one t o the drain and one t o the gate. the results are strikingly different. At room temperature. the behaviour seen is the expected INCREASE in drive current (squares). I n the case o f the a.c. stress at 125 "C. the device shows a DECREASE in drive current w i t h time (circles). This is due t o the combination o f N B T I during drain low - gate high stresses, and switching, when b o t h drain and gate are high, leading t o H ( T D G ) .

CONCLUSIONS H o t carrier stresses at high temperatures and at Vg=Vd

has been performed in order t o study the interaction o f N B T l on hot carriers. The results show t h a t the resultant effect (H(TDG)) accelerates considerably the NBTl damage, by up t o a factor o f IO. The acceleration is explained in terms o f the role o f holes i n the creation o f NBTI-type damage. Finally, a.c. stress measurements show t h a t CHE dominates at 25 "C. while H ( T D G ) effects are dominant at 125 "C.

ACKNOWLEGEMENTS The authors would like t o thank Vlad Bolkovsky and the

members of his team for the devices used.

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111

I21

131

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151

171

191

161

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I111 I121 1131

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B.Doyle and K.Mistry. IEEE Trans. Electron Dev. ED- 37. 1301. 1990 D.J.Breed Appl. Phys. Lett. vol. 26. 116.1975 P.Rosse1 et al.. Solid State El. vol. 13. 425. 1970 S.R.Hofstein. Solid State El. vol. IO. 657. 1967 J.Bennet and L.M.Roth J. Phys. Chem. Solids vol. 32, 1251. 1971. D.Lu et al., Appl. Phys. Lett. vol. 52. 1344. 1988. S.K.Lai J.Appl. Phys. vol. 54. 2540, 1983 K.O.Jeppson and C.M.Svensson J.Appl. Phys. vol. 48. 2004. 1977

vol. ED-35, 320. 1988.

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