VHDL

I'll have open note test on Thursda7, March 10

its a VHDL class and the test will be emphasis on Boolean algebra, numerical and data representation, 2's complement, Karnaugh maps, Combinational circuit designs, Dataflow, Behavioral, and Structural design styles, timing delays, and test benches.

chapter 1 to 4 from book "fundamentals of digi and computer design with VHDL" the book cover  uploaded 

communicating in direct app would much better.