ECET-230 – Digital Circuits and Systems Homework Assignment #4

Name

1.      What is the output frequency of Q1 in the circuit shown below?

2.      A synchronous binary counter is used to divide a 1 MHz input frequency to 3.90625 kHz. What is the MOD number of the counter and how many flip-flops are required?

3.      If the MOD-8 binary counter is driven by a 10 MHz input clock with a 5% duty cycle, what is the output frequency and duty cycle of the final stage?

4.      Determine the output frequency for the cascaded counter configuration shown below.

Design a circuit that will convert a 2 MHz input frequency to a .5 MHz output frequency.  You may submit a Multisim worksheet or a neatly hand-written schematic.

9&10.  Write the VHDL code to design the counter from the last slide of the Week #4 lecture that produces the following counting sequence:  12-13-14-15-16-17-12-13…