Digital Logic Design - Question about Timing Diagram

I need this question done by tomorrow night Wednesday July 29 8PM USA Central Time.

There is only one question with 5 parts. You are given a timing diagram and must derive truth table, minterm + maxterm list, and draw NAND and NOR outcome.

Review the assignment in the attached file and be sure you can complete it in time before send me a handshake request or messaging. 

Don't bother contacting if you have zero or many negative reviews. I will not reply.