Computer Science Homework - MIPS Instruction Set Architecture

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Homework 6 -MIPS Instruction Set Architecture Problem 6.1 MIPS Arithmetics (4 points) Perform the following arithmetic operations by giving MIPS code: 1. a = b + c 2. a = b ?? c + d 3. a = 8 b 4. a = (2 + b) 4 Please assume that a is in register $t0, b in register $s0, c is in register $s1 and d is in $s2.. Keep in mind that you do not know the mul operation yet. Also, comment each relevant code block. Problem 6.2 Binary codes for instructions (2 points) Give binary codes of the MIPS instructions for the operations 1 and 2 of the previous problems. Problem 6.3 Memory access in MIPS (1 point) Suppose you write the following C code: B[5] = A[2] + A[3] 1. Please write down the MIPS assembler code for this code. Assume that the address of base of A is stored in $s0, the base of B is stored in $s1. Comment the relevant code blocks. Problem 6.4 Memory access using a variable index (2 points) Suppose you write the following C code: B[x] = A[x + 2] + A[x + 3] 1. Please write down the MIPS assembler code for this code. Assume that the address of base of A is stored in $s0, the base of B is stored in $s1 and the value of x in $t0 Comment the relevant code blocks. Problem 6.5 MIPS Instruction format I (1 point) The register instruction format for the instruction addi uses 6 bits for the opcode, 5 bits for the first register, 5 bits for the second register. and 16 bits for the constant value that is to be added. A detailed analysis of machine code has revealed that not more than 12 registers are needed for the processor and therefore it has been decided to reduce the number of general purpose registers to 16. How and why could the instruction format for the addi instruction be changed?