Assume that individual stages of the datapath have the latencies shown below, and answer the questions below. Hint: see Figure...

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  1. Assume that individual stages of the datapath have the latencies shown below, and answer the questions below. Hint: see Figure 4.27 of textbook.

Instruction

Instruction fetch

Register read

ALU op

Memory access

Register write

lw

150 ps

100 ps

180 ps

150 ps

100 ps

sw

150 ps

100 ps

180 ps

150 ps

 

R-type

150 ps

100 ps

180 ps

 

100 ps

beq

150 ps

100 ps

180 ps

 

 

a)      What is the clock cycle time in a single-cycle processor and a pipelined processor?

b)     What is the total latency of executing 1000 instructions in sequence in a single-cycle processor and in a pipelined processor? Assume no stalls or hazards.

 

  1. Show the portion of the datapath in Figure 4.41 that is used in all stages of executing a branching instruction (e.g., beq). See Figure 4.42 for an example.
  2. Consider the execution of a MIPS load-word (lw) instruction and specify the content of each pipeline register during the execution of this instruction in a pipelined CPU shown in Figure 4.51 of textbook. Provide answers in the following format – list the names and sizes (i.,e., number of bits) all data fields and control signal fields that are latched to each pipeline register between two stages (e.g., IF/ID, ID/EX, EX/MEM, MEM/WB) and, in the list, underline the data and control signal fields that are actually used in the execution of the load-word instruction. An example format of an answer is as follows.
  • X/Y register:
    • n1-bit control.signals for the Y stage
    • n2-bit data field1 (e.g., register number, value read from the register, ALU output)
    • n3-bit data field1 (e.g., register number, value read from the register, ALU output)

For control signals, it is sufficient to name the fields labeled in Figure 4.50 (i.e., EX, M, WB) instead of the individual signal names.

  1. Given the following sequence of MIPS instructions, state where data hazards occur, if any, and show the forwarding needed to remove or reduce the CPU stalls due to data hazards. Show the forwarding and/or stalls using graphical representations like Figure 4.29 (page 279) and Figure 4.30 (page 280).

add $3, $4, $6

sub $5, $3, $2

lw $7, 100($5)

add $8, $7, $2

 

 

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