Need help on computer organization and architecture course.

You will perform calculations comparing the performance of two computer systems, Machine A and Machine B, against two separate benchmark programs, I and II.  Table 2.1 gives the clock rates for Machines A and B, along with the number of clock cycles required to execute each type of instruction.  Table 2.2 gives the number of instructions (in millions) required to run each benchmark program for each of the two machines.  The reference run times (Tref) for benchmarks I and II are 50 ms and 70 ms, respectively.

Your task is to evaluate and compare Machine A vs. Machine B for the two benchmarks by completing Table 2.3.  As you click on cells in Table 2.3, a large green box will appear on the right to help guide you through the problem.

Table 2.1: Clock rate and Cycles per Instruction
Machine	A	B
Clock Rate	1.8 GHz	3.0 GHz
Arithmetic and Logic	1	1
Load/Store	3	5
Branch	4	3
Other	2	3

Table 2.2: Instruction Counts for benchmarks I and II (millions)
Machine	A	B
Benchmark	I	II	I	II
Arithmetic and Logic	8	6	7	5
Load/Store	5	7	5	10
Branch	3	5	4	4
Other	4	4	2	3

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Table 2.3: Benchmark Comparison
Machine	A	B
Clock period (ps)	image1.wmf	image2.wmf
Benchmark	I	II	I	II
Instruction Count (millions)	image3.wmf	image4.wmf	image5.wmf	image6.wmf
Average Cycles per Instruction	image7.wmf	image8.wmf	image9.wmf	image10.wmf
Execution time (ms)	image11.wmf	image12.wmf	image13.wmf	image14.wmf
MIPS	image15.wmf	image16.wmf	image17.wmf	image18.wmf
Speed ratio	image19.wmf	image20.wmf	image21.wmf	image22.wmf
SPEC speed metric	image23.wmf	image24.wmf
Faster Clock Frequency image25.png	image26.wmf	image27.wmf	image28.wmf B
Faster Machine image29.png	image30.wmf	image31.wmf	image32.wmf B

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Question #1 – CPU Components

Which of the following are components of the CPU?

a.		system bus
b.		I/O module
c.		main memory
d.		I/O buffers
e.		instruction register
f.		registers for accessing I/O devices
g.		registers for accessing memory
h.		program counter
i.		execution unit

Question #2 – IAS Instruction Format

[Modified from Stallings Problem 2.2]

For the Institute for Advanced Studies (IAS) computer from Princeton (see photo at right), use Fig. 2.2 and Table 2.1 from your textbook to determine the following machine code:

Left instruction – take the next instruction from the left half of M(224) Right instruction – transfer the negative of the absolute value of M(282) to AC

M(X) refers to the data at memory location X, where X is expressed as a 3 digit hexadecimal value.  Express your answer in binary.

Table 2.1 – IAS Instruction
LEFT	RIGHT
Op Code	Address	Op Code	Address
image35.wmf	image36.wmf	image37.wmf	image38.wmf

Question #3 – IAS Program

[Modified from Stallings Problem 2.4] Consider the IAS code fragment shown below in Table 3.1.  Six instructions are located at 3 consecutive memory addresses (See Stallings Fig. 2.2b for the instruction format).  Using Table 2.1 from your textbook, translate the 40-bit hexadecimal values in Table 3.1 to their corresponding assembly language instructions.  Notice that the value 'X' needs to replaced with a 3-digit address for those instructions in which the 'X' appears.  A few examples of legal syntax assembly language instructions are shown in Table 3.2 below.

Notes:

1. All of the data and addresses are in hexadecimal.

2. The IAS computer stores negative numbers in signed-magnitude format (see Fig. 2.2a in your textbook).  The MSB (Most Significant Bit) is 0 for positive numbers and 1 for negative numbers.  The remaining 39 bits give the magnitude.  Notice how this format differs from 2's complement format.

3. Unless a JUMP instruction is encounted, the IAS first executes the LEFT instruction, then the RIGHT instruction, then proceeds to the next address.

Table 3.1 – IAS Code Fragment
Address	Contents (hex)	LEFT	RIGHT
047	0113E2113F	image39.wmf	image40.wmf
048	090501004A	image41.wmf	image42.wmf
049	0213E2113F	image43.wmf	image44.wmf

Table 3.2 – Sample IAS instruction Syntax
LEFT	RIGHT
LOAD M(A39)	JUMP+M(0F8,0:19)
ADD |M(2A3)|	LSH
MUL M(8E0)	STOR M(49C,28:39)

Now assume the program counter begins at 047:LEFT, and that the value stored at memory location 13E is 90C959CE09.  Complete the following statements about what happens when the code fragment executes:

a. The instruction at location 049:RIGHT be executed. Will or will not?

b. The value stored at memory location 13E after program completion will be

.

c. The value stored at memory location 13F after program completion will be

.

d. The value stored in the accumulator after program completion will be

.

e. After execution, the program counter is at

: and is it left or right?

Again assuming the program counter begins at 047:LEFT, but now that the value stored at memory location 13E is 10C959CE09.  Complete the following statements about what happens when the code fragment executes:

a. The instruction at location 049:LEFT be executed. Will or will not?

b. The value stored at memory location 13E after program completion will be

.

c. The value stored at memory location 13F after program completion will be

.

d. The value stored in the accumulator after program completion will be

.

e. After execution, the program counter is at

: and is it left or right?

Question #4 – Data transfer

A. Describe two causes for performance degradation of a single-bus design as the number of devices connected to the bus increases.

1.

2.

B. How does point-to-point interconnect differ from a shared bus?

Question #5 – Transfer Rate

[Modified from Stallings Problem 3.5] Consider a 32-bit microprocessor with a 64-bit external data bus that is driven by an input clock running at 132 MHz.  Assume this microprocessor has a bus cycle whose duration equals five input clock cycles.

A. What is the bus cycle rate?

bus cycles/sec

B. How many bytes are transferred each bus cycle?

bytes/bus cycle

C. What is the maximum data transfer rate?

bytes/sec