Digital Circuit Project

module tb; reg A,B,C,D; wire [0:3] Y; Change_Controller c1 (A,B,C,D,Y); initial begin #10 {A,B,C,D} = 4'b0000; #10 {A,B,C,D} = 4'b0001; #10 {A,B,C,D} = 4'b0010; #10 {A,B,C,D} = 4'b0011; #10 {A,B,C,D} = 4'b0100; #10 {A,B,C,D} = 4'b0101; #10 {A,B,C,D} = 4'b0110; #10 {A,B,C,D} = 4'b0111; #10 {A,B,C,D} = 4'b1000; #10 {A,B,C,D} = 4'b1001; end endmodule