Computer Architecture Verilog

// ----------------------------------------------------------------------- // // Computer Architecture Project 2 // Spring 2018 // Author: John Stubban // Description: // - This verilog-2005 module wraps a testbench around an // asynchronous FIFO module. // - The simulation will finish by itself after 400 read clocks (line65). // - The simulation will output a value change dump file which can be // opened by GTKWave or similar waveform viewer named "fifo.vcd". // ----------------------------------------------------------------------- // `timescale 1ns/1ns module tb_fifo ; // FIFO Parameters parameter ASIZE = 4; // Fifo depth as 2^ASIZE parameter WRITE_BURST = 16; // write 16 bytes of data parameter BURST_INTERVAL=100; // 100 write clocks // FIFO Clocking speeds parameter W_PERIOD = 200, // 5 MHz ( (1/5E6) * 1/(1E-9)=200 from `timescale on line 11) R_PERIOD = 1000; // 1 MHz // Variables parameter DSIZE = 8; // Data bit width reg wclk, rclk; // write/read clock reg winc; // write clock enable wire rinc; wire wfull, rempty; // write/read fifo full, empty reg wrst_n, rrst_n; // resets reg [DSIZE-1:0] wdata;// write data wire [DSIZE-1:0] rdata;// read data wire reg [DSIZE-1:0] last_rdata; reg fail; integer burst_cnt=0; // FIFO under test fifo1 #(DSIZE, ASIZE) DUT1 ( .rdata(rdata), .wfull(wfull), .rempty(rempty), .wdata(wdata), .winc(winc), .wclk(wclk), .wrst_n(wrst_n), .rinc(rinc), .rclk(rclk), .rrst_n(rrst_n)); initial begin $dumpfile("fifo.vcd"); $dumpvars; burst_cnt=0; fail = 0; // initialize the clocks wclk=0; rclk=0; winc=0; // init data wdata= 8'hFF; last_rdata = 8'hFF; // Power on reset wrst_n=0; rrst_n=0; repeat(10) @ (posedge rclk); // wait 10 read clocks wrst_n=1; //reset off rrst_n=1; // reset off repeat(400) @ (posedge rclk); if (fail) $display("Simulation Failed"); else $display("Simulation Passed"); $finish; end//intital // Set clocks, 50% duty-cycle always begin #(W_PERIOD/2); wclk = ~wclk; end always begin #(R_PERIOD/2); rclk = ~rclk; end //assign #50 wclk = ~wclk; //assign #125 rclk = ~rclk; // Write Burst always @ (posedge wclk) begin:wr if (wrst_n & (burst_cnt < WRITE_BURST) ) begin winc = 1'b1; wdata = wdata + 1'b1; burst_cnt = burst_cnt + 1; end//if else begin wdata = wdata; winc = 1'b0; burst_cnt = 0; repeat (BURST_INTERVAL) @ (posedge wclk); end//else end//always assign rinc = (~rempty ) ? 1'b1 : 1'b0; always @ (posedge rclk) begin if (rinc) begin if ((last_rdata + 8'h01) == rdata) begin $display ("%h", rdata); last_rdata = rdata; end else begin $display("FAIL: %h != %h", (last_rdata + 8'h01), rdata); fail = 1; last_rdata = rdata; end end end endmodule