Cache simulator
Sample Testing/multi_sample1_config
2 230 8 16 3 1 0 13 8 32 3 1 0 40
Sample Testing/multi_sample1_trace
==multi_sample1_config has an L1 with 16 bytes (13 cycles), L2 with 32 bytes (40 cycles), RAM is 230 cycles L 0,4 L 80,8 L 10,4 L 102,6 L 2,6 ==The following store involves a "fetch on write" operation because we had to fetch the original block first S 180,5 L 100,2 ==Note that the following load is spread across two blocks: L 4,20 L 100,2 L 80,8 M 180,6 L 100,8 S 100,5 S 180,8 L 80,8 M 0,8 M 0,4 L 280,4 M 80,8
Sample Testing/multi_sample1_trace.zip
multi_sample1_trace.out
| L 0 | 4 286 L1 miss L2 miss |
| L 80 | 8 286 L1 miss L2 miss |
| L 10 | 4 53 L1 miss L2 hit |
| L 102 | 6 286 L1 miss L2 miss |
| L 2 | 6 13 L1 hit |
| S 180 | 5 572 L1 miss eviction L2 miss hit |
| L 100 | 2 13 L1 hit |
| L 4 | 20 26 L1 hit |
| L 100 | 2 13 L1 hit |
| L 80 | 8 53 L1 miss eviction L2 hit |
| M 180 | 6 53 L1 miss eviction L2 hit |
| M 180 | 6 286 L1 hit L2 hit |
| L 100 | 8 13 L1 hit |
| S 100 | 5 286 L1 hit L2 hit |
| S 180 | 8 286 L1 hit L2 hit |
| L 80 | 8 13 L1 hit |
| M 0 | 8 53 L1 miss eviction L2 hit |
| M 0 | 8 286 L1 hit L2 hit |
| M 0 | 4 13 L1 hit |
| M 0 | 4 286 L1 hit L2 hit |
| L 280 | 4 286 L1 miss eviction L2 miss |
| M 80 | 8 13 L1 hit |
| M 80 | 8 286 L1 hit L2 hit |
| L1 Cache: Hits:15 Misses:9 Evictions:5 | |
| L2 Cache: Hits:11 Misses:5 Evictions:0 | |
| Cycles:3761 Reads:16 Writes:7 |
Sample Testing/multi_sample2_config
3 230 8 16 3 1 0 13 8 32 2 1 0 40 32 32 3 1 0 110
Sample Testing/multi_sample2_trace
== multi_sample2_configuration == L1: 16 bytes/block, 8 sets, associativity N=3, LRU, 13 cycles == L2: 32 bytes/block, 8 sets, associativity N=2, LRU, 40 cycles == L3: 32 bytes/block, 32 sets, associativity N=3, LRU, 110 cycles == RAM: 230 cycles L 474,1 L 460,8 S 47c,16 M 7,8 L c7e,2 == this store will hit L2 while fetching: S c68,8 L 864,10 L 460,8 == the following load is more complex due to multiple cache impacts... L 60,4
Sample Testing/multi_sample2_trace.zip
multi_sample2_trace.out
L 474,1 396 L1 miss L2 miss L3 miss L 460,8 53 L1 miss L2 hit S 47c,16 959 L1 miss hit L2 miss hit L3 miss hit M 7,8 396 L1 miss L2 miss L3 miss M 7,8 396 L1 hit L2 hit L3 hit L c7e,2 396 L1 miss L2 miss L3 miss S c68,8 449 L1 miss L2 hit L3 hit L 864,10 396 L1 miss L2 miss eviction L3 miss L 460,8 13 L1 hit L 60,4 396 L1 miss eviction L2 miss eviction L3 miss eviction L1 Cache: Hits:3 Misses:8 Evictions:1 L2 Cache: Hits:6 Misses:6 Evictions:2 L3 Cache: Hits:4 Misses:6 Evictions:1 Cycles:3850 Reads:7 Writes:3
Sample Testing/sample1_config
1 230 8 8 3 1 0 13
Sample Testing/sample1_trace
==Note that sample1_config is designed to hold only 8 bytes per block L 0,4 L 80,8 L 10,4 L 102,6 L 2,6 ==The following store involves a "fetch on write" operation because we had to fetch the original block first S 180,5 L 100,2 ==Note that the following load is spread across three blocks == (see next command) ==Blocks 0 and 2 are still in the cache, but block 1 has never been loaded ==Technically this causes an L1 "hit miss hit" but it is fine if your output file just indicates ==that there was at least one hit and miss ("L1 miss hit" or "L1 hit miss"). The ordering does not matter as long as ==you correctly indicate their presence. ==The important thing is that ALL block hits and misses are reflected in the statistics that are printed at the ==very end of the output file. L 4,20 L 100,2 L 80,8 M 180,6 L 100,8 S 100,5 S 180,8 L 80,8 M 0,8 M 0,4 L 280,4 M 80,8
Sample Testing/sample1_trace.zip
sample1_trace.out
| L 0 | 4 243 L1 miss |
| L 80 | 8 243 L1 miss |
| L 10 | 4 243 L1 miss |
| L 102 | 6 243 L1 miss |
| L 2 | 6 13 L1 hit |
| S 180 | 5 486 L1 miss eviction |
| L 100 | 2 13 L1 hit |
| L 4 | 20 269 L1 miss hit |
| L 100 | 2 13 L1 hit |
| L 80 | 8 243 L1 miss eviction |
| M 180 | 6 243 L1 miss eviction |
| M 180 | 6 243 L1 hit |
| L 100 | 8 13 L1 hit |
| S 100 | 5 243 L1 hit |
| S 180 | 8 243 L1 hit |
| L 80 | 8 13 L1 hit |
| M 0 | 8 243 L1 miss eviction |
| M 0 | 8 243 L1 hit |
| M 0 | 4 13 L1 hit |
| M 0 | 4 243 L1 hit |
| L 280 | 4 243 L1 miss eviction |
| M 80 | 8 13 L1 hit |
| M 80 | 8 243 L1 hit |
| L1 Cache: Hits:15 Misses:10 Evictions:5 | |
| Cycles:4248 Reads:16 Writes:7 |
Sample Testing/sample2_config
1 230 8 32 3 1 0 13
Sample Testing/sample2_trace
| ==Note that sample2_config is designed to hold 32 bytes per block | |
| ==This has several effects | one of which is that the RAM requires (230+1+1+1) cycles to fetch a 32 byte block. |
| ==Another side effect is that the blocks do not all fall into the same index (hence the lack of evictions). | |
| L 0 | 4 |
| L 80 | 8 |
| L 10 | 4 |
| L 102 | 6 |
| L 2 | 6 |
| S 180 | 5 |
| L 100 | 2 |
| L 4 | 20 |
| L 100 | 2 |
| L 80 | 8 |
| M 180 | 6 |
| L 100 | 8 |
| S 100 | 5 |
| S 180 | 8 |
| L 80 | 8 |
| M 0 | 8 |
| M 0 | 4 |
| L 280 | 4 |
| M 80 | 8 |
Sample Testing/sample2_trace.zip
sample2_trace.out
| L 0 | 4 246 L1 miss |
| L 80 | 8 246 L1 miss |
| L 10 | 4 13 L1 hit |
| L 102 | 6 246 L1 miss |
| L 2 | 6 13 L1 hit |
| S 180 | 5 492 L1 miss |
| L 100 | 2 13 L1 hit |
| L 4 | 20 13 L1 hit |
| L 100 | 2 13 L1 hit |
| L 80 | 8 13 L1 hit |
| M 180 | 6 13 L1 hit |
| M 180 | 6 246 L1 hit |
| L 100 | 8 13 L1 hit |
| S 100 | 5 246 L1 hit |
| S 180 | 8 246 L1 hit |
| L 80 | 8 13 L1 hit |
| M 0 | 8 13 L1 hit |
| M 0 | 8 246 L1 hit |
| M 0 | 4 13 L1 hit |
| M 0 | 4 246 L1 hit |
| L 280 | 4 246 L1 miss |
| M 80 | 8 13 L1 hit |
| M 80 | 8 246 L1 hit |
| L1 Cache: Hits:18 Misses:5 Evictions:0 | |
| Cycles:3108 Reads:16 Writes:7 |
Sample Testing/sample3_config
1 230 8 32 3 1 0 13
Sample Testing/sample3_trace
== Note that sample3_config is designed to hold 32 bytes per block == Demonstrate the RAM buffering behavior L 0,4 L 1f,1 L 20,1
Sample Testing/sample3_trace.zip
sample3_trace.out
L 0,4 246 L1 miss L 1f,1 13 L1 hit L 20,1 17 L1 miss L1 Cache: Hits:1 Misses:2 Evictions:0 Cycles:276 Reads:3 Writes:0