re-do the circuit using Multisim
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Title
Number RevisionSize
B
Date: 8/27/2015 Sheet of File: Y:\JYU_PERSONAL\..\CSUF_EE310_TEST_01_P01_REV_X01.SchDocDrawn By:
DATE REV DESCRIPTION
06/07/2015
X01
PAGE: 01
CSUF_EE310_LAB01 X01
OP-AMP IC CHARACTERISTICS
1) 06/01/2015, PROCEED TO PCB LAYOUT REVISION X01
1 1
MN2 156D_280P_MNT
1 1
MN3 156D_280P_MNT
1 1
MN4 156D_280P_MNT
1 1
MN1 156D_280P_MNT
1 1
FD1
FIDUCIAL
1 1
FD2
FIDUCIAL
1 1
FD3
FIDUCIAL
1 1
FD4
FIDUCIAL
2) 2015-06-07, RELEASE TO PROTOTYPE
ECN #
1 1PCB_PN PCB1
CSUF_EE310L_TEST_01_REV_X01
CHGND
FILE: CSUF_EE310_TEST_01_P01_REV_X01
COMPLETE PCB LAYOUT REV X01 - RELEASE TO PROTOTYPE
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Title
Number RevisionSize
B
Date: 8/27/2015 Sheet of File: Y:\JYU_PERSONAL\..\CSUF_EE310_TEST_01_P02_REV_X01.SchDocDrawn By:PAGE: 02
OP-AMP IC CHARACTERISTICS
CSUF_EE310_LAB01 X01
FILE: CSUF_EE310_TEST_01_P02_REV_X01
PAGE 02 - RESERVED
1
1
2
2
3
3
4
4
5
5
6
6
D D
C C
B B
A A
Title
Number RevisionSize
B
Date: 8/27/2015 Sheet of File: Y:\JYU_PERSONAL\..\CSUF_EE310_TEST_01_P03_REV_X01.SchDocDrawn By:
FILE: CSUF_EE310_TEST_01_P03_REV_X01 PAGE: 03
OP-AMP IC CHARACTERISTICS
CSUF EE310 LAB01 X01
V +
7
NON-INV_INP3
V -
4
OUTPUT 6
OFFSET_NULL 1
OFFSET_NULL 5
N C
8
INV_INP2
OPAMP_1 LM741
1
V+1
575-4
1
V-1
575-4
1
GND1
575-4
VS+
GND
VS-
VS+
VS-
RA1
200K RA2
200K
RB1
1K
55 33 11
6 6 4 4 2 22X4_100SPC
77 8 8
CN1
2X4PIN_100SPC_HDR
11 2 2
JMP3 1X2PIN_100SPC_HDR
11 2 2
JMP4 1X2PIN_100SPC_HDR
VIN_INV
VIN_NON_INV
RC1
10K
CA1
1uF_TH
CA2
1uF_TH
GND
GND
GND
VOUT
11 2 2
JMP1 1X2PIN_100SPC_HDR
11
TP5 62.5D_TEST_PIN
11
TP5G 62.5D_TEST_PIN
GND1 1
TP3 62.5D_TEST_PIN
1 1
TP4 62.5D_TEST_PIN
1 3
C C
W C
W
2
W IP
E R
POT1 10K_POT
1 1
2 2
3 3
JMP6 1X3PIN_100SPC_HDR
GND VS-
RB2
1K
11 2 2
JMP2
1X2PIN_100SPC_HDR
1 1
2 2
JM P7
1X 2P
IN _1
00 SP
C _H
D R
1 1
2 2
JM P8
1X 2P
IN _1
00 SP
C _H
D R
GND GND
1 1 TP1
TP1
1 1 TP2G
62.5D_TEST_PIN
1 1
2 2
JM P5
1X 2P
IN _1
00 SP
C _H
D R
GND
GND
11 2 2
JMP9 1X2PIN_100SPC_HDR
RD1 100K
RD2 100K
1 3
C C
W C
W
2
W IP
E R
POT2 10K_POT
VS+
VS-
11 2 2
JMP10 1X2PIN_100SPC_HDR
1 1 TP1B
TP1
1 1
TP4G 62.5D_TEST_PIN
1 1
TP3G 62.5D_TEST_PIN
GND GND
1 2
LED1 LED_GRNRB3
1K
GND
VS+