digital electronics
labcpu/clkdiv.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity clkdiv is generic(N : integer); port ( clkin : in STD_LOGIC; clkout : out STD_LOGIC ); end clkdiv; architecture Behavioral of clkdiv is signal divider : STD_LOGIC_VECTOR(N-1 downto 0); begin process(clkin) begin if rising_edge(clkin) then divider<=divider+1; end if; end process; clkout<=divider(N-1); end Behavioral;
labcpu/cpu.vhd
---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cpu is generic(N : integer); port( clk : in STD_LOGIC; rst : in STD_LOGIC; ext_in : in STD_LOGIC_VECTOR(7 downto 0); ext_out : out STD_LOGIC_VECTOR(7 downto 0); ram_we : out STD_LOGIC; ram_address : out STD_LOGIC_VECTOR(N-1 downto 0); ram_datawr : out STD_LOGIC_VECTOR(7 downto 0); ram_datard : in STD_LOGIC_VECTOR(7 downto 0); -- Only for debugging dbg_qa : out STD_LOGIC_VECTOR(7 downto 0); dbg_qb : out STD_LOGIC_VECTOR(7 downto 0); dbg_qc : out STD_LOGIC_VECTOR(7 downto 0); dbg_qd : out STD_LOGIC_VECTOR(7 downto 0); dbg_instr : out STD_LOGIC_VECTOR(15 downto 0); dbg_seq : out STD_LOGIC_VECTOR(1 downto 0); dbg_flags : out STD_LOGIC_VECTOR(3 downto 0) ); end cpu; architecture Behavioral of cpu is -- Instruction signal instruction : STD_LOGIC_VECTOR(15 downto 0); -- Helper signal source : STD_LOGIC_VECTOR(7 downto 0); signal wrdata : STD_LOGIC_VECTOR(7 downto 0); -- register bank signal regwren : STD_LOGIC; signal reg1out : STD_LOGIC_VECTOR(7 downto 0); signal reg2out : STD_LOGIC_VECTOR(7 downto 0); -- flags signal flagwren : STD_LOGIC; signal flags : STD_LOGIC_VECTOR(3 downto 0); -- zf, ovf, cf, sf signal zf,ovf,cf,sf : STD_LOGIC; -- fetch/execute signals signal seq : STD_LOGIC_VECTOR(1 downto 0); signal execute,fetch,fetchh,fetchl : STD_LOGIC; -- Instruction pointer signal ip: STD_LOGIC_VECTOR(N-1 downto 0); signal ipnext: STD_LOGIC_VECTOR(N-1 downto 0); -- ALU input and output signals signal aluqout: STD_LOGIC_VECTOR(7 downto 0); signal alufout : STD_LOGIC_VECTOR(3 downto 0); -- Jumps signal jump : STD_LOGIC; signal jumpip: STD_LOGIC_VECTOR(N-1 downto 0); signal jumpconditionvalid : STD_LOGIC; -- External interface signal ext_wren : STD_LOGIC; -- Debug signals --signal tdbg_qa,tdbg_qb,tdbg_qc,tdbg_qd : STD_LOGIC_VECTOR(7 downto 0); begin --------------------------------------------------------------------------------------- -- Fetch/Execute -- Fetch/Execute -- Fetch/Execute -- Fetch/Execute -- Fetch/Execute -- --------------------------------------------------------------------------------------- -- Instantiate a fetch/exec sequencer. Seq is 00 for load1, 01 for load2, 10 for execute comp_seq: entity work.cpusequencer port map(clk=>clk,rst=>rst,en=>'1',seq=>seq); -- Binary to one hot fetchh <= '1' when seq="00" else '0'; fetchl <= '1' when seq="01" else '0'; execute <= '1' when seq="10" else '0'; fetch <= fetchl or fetchh; -- Instantiate two 8-bit registers to store the 16-bit instruction during the fetchl and fetchh cycles. comp_instrh: entity work.dffre generic map(N=>8) port map(clk=>clk,rst=>rst,en=>fetchh,d=>ram_datard,q=>instruction(15 downto 8)); comp_instrl: entity work.dffre generic map(N=>8) port map(clk=>clk,rst=>rst,en=>fetchl,d=>ram_datard,q=>instruction(7 downto 0)); --------------------------------------------------------------------------------------- -- Instruction pointer --------------------------------------------------------------------------------------- comp_ip: entity work.dffre generic map(N=>N) port map(clk=>clk,rst=>rst,en=>'1',d=>ipnext,q=>ip); ipnext <= ip+1 when fetch='1' else ip when jump='0' else jumpip; --------------------------------------------------------------------------------------- -- Register bank -- Register bank -- Register bank -- Register bank -- Register bank -- --------------------------------------------------------------------------------------- -- Instantiate the register bank -- Always map the register 1 and register 2 to the source and destination registers in the instruction fields -- Always map the write register to destination register in instruction field. -- Always map the write input to wrdata comp_regs: entity work.cpuregbank port map(clk=>clk,rrd1=>instruction(9 downto 8),rrd2=>instruction(1 downto 0),rwr=>instruction(9 downto 8),rwren=>regwren,rst=>rst,d=>wrdata,q1=>reg1out,q2=>reg2out, dbg_qa=>dbg_qa,dbg_qb=>dbg_qb,dbg_qc=>dbg_qc,dbg_qd=>dbg_qd); -- Write to register for move instructions with direct destination, or ALU instructions except cmp. regwren <= '1' when execute='1' and instruction(15 downto 13) = "000" and instruction(11)='0' else -- opcode 000 (move) '1' when execute='1' and instruction(15 downto 13) = "001" else -- opcode 001 (add,sub,and,or) '1' when execute='1' and instruction(15 downto 13) = "010" and instruction(11 downto 10) /= "01" else -- opcode 010 (all except cmp) '1' when execute='1' and instruction(15 downto 13) = "011" else -- opcode 011 '1' when execute='1' and instruction(15 downto 13) = "110" and instruction(11 downto 10) = "01" else -- opcode 110 (io) '0'; -------------------------------------------------------------------------------------------- -- Helper -- Helper -- Helper -- Helper -- Helper -- Helper -- Helper -- Helper -- Helper -- -------------------------------------------------------------------------------------------- -- Almost all instructions using a source have register or immediate mode. We source <= reg2out when instruction(12)='0' else instruction(7 downto 0); ------------------------------------------------------------------------------- -- ALU -- ALU -- ALU -- ALU -- ALU -- ALU -- ALU -- ALU -- ALU -- ALU -- ALU -- ------------------------------------------------------------------------------- -- Instantiate ALU comp_alu: entity work.cpualu port map(clk=>clk,rst=>rst,op=>instruction(14 downto 10),a=>reg1out,b=>source,q=>aluqout,f=>alufout); ----------------------------------------------------------------------------------- -- Flags -- Flags -- Flags -- Flags -- Flags -- Flags -- Flags -- Flags -- Flags -- ----------------------------------------------------------------------------------- -- instantiate register to store the flags comp_flags: entity work.dffre generic map(N=>4) port map(clk=>clk,rst=>rst,en=>flagwren,d=>alufout,q=>flags); -- When to write the flags: execute phase and compare instruction flagwren <= '1' when execute='1' and instruction(15 downto 13)="010" and instruction(11 downto 10)="01" else '0'; -- Individual signals for each flag zf <= flags(3); ovf <= flags(2); cf <= flags(1); sf <= flags(0); ----------------------------------------------------------------------------------- -- Jump -- Jump -- Jump -- Jump -- Jump -- Jump -- Jump -- Jump -- Jump -- Jump -- ----------------------------------------------------------------------------------- -- Jump destinatinon is register or immediate jumpip <= source(N-1 downto 0); -- Do jump when the instruction is a jump and the jump condition is met jump <= '1' when instruction(15 downto 13) = "101" and jumpconditionvalid='1' else '0'; -- Jump condition jumpconditionvalid <= '1' when instruction(11 downto 8) = "0000" else -- Unconditional jump '1' when instruction(11 downto 8) = "0001" and zf='1' else -- je/jz '1' when instruction(11 downto 8) = "1001" and zf='0' else -- jne/jnz '1' when instruction(11 downto 8) = "0010" and zf='0' and cf='0' else -- ja '1' when instruction(11 downto 8) = "1011" and zf='0' and cf='1' else -- jb '0'; --------------------------------------------------------------------------------------- -- RAM interface -- RAM interface -- RAM interface -- RAM interface -- RAM interface -- --------------------------------------------------------------------------------------- -- ram address to read instruction and read or write data ram_address <= ip when fetch='1' else reg2out(N-1 downto 0) when instruction(15 downto 10)="000001" else instruction(N-1 downto 0) when instruction(15 downto 10)="000101" else reg1out(N-1 downto 0) when instruction(15 downto 10)="000010" else reg1out(N-1 downto 0) when instruction(15 downto 10)="000110" else (others=>'0'); --"00000"; -- Enable write ram_we <= '1' when execute='1' and instruction(15 downto 13)="000" and instruction(11 downto 10)="10" else '0'; -- Data to write ram_datawr <= wrdata; ------------------------------------------------------------------------------------------ -- External interface -- External interface -- External interface -- External interface -- ------------------------------------------------------------------------------------------ -- Instantiate a register to hold the output interface data comp_regextout : entity work.dffre generic map (N=>8) port map(clk=>clk,rst=>rst,en=>ext_wren,d=>source,q=>ext_out); ext_wren <= '1' when execute='1' and instruction(15 downto 13) = "110" and instruction(11 downto 10)="00" else '0'; -------------------------------------------------------------------------------------- -- Write data -- Write data -- Write data -- Write data -- Write data -- Write data -- -------------------------------------------------------------------------------------- -- Data may be written to ram or memory. The enable signals in the ram and register instances -- control whether the write occurs. -- Here we define what to write. wrdata <= source when instruction(15 downto 13) = "000" and instruction(11 downto 10)="00" else -- Move with register or immediate as source source when instruction(15 downto 13) = "000" and instruction(11 downto 10)="10" else -- Move with register or immediate as source ram_datard when instruction(15 downto 13) = "000" and instruction(11 downto 10)="01" else -- Move with memory as source aluqout when instruction(15 downto 13) = "001" else -- ALU aluqout when instruction(15 downto 13) = "010" else -- ALU aluqout when instruction(15 downto 13) = "011" else -- ALU ext_in when instruction(15 downto 13) = "110" and instruction(11 downto 10)="01" else -- Instruction in: read external input "00000000"; -- Only for debugging dbg_instr <= instruction; dbg_seq <= seq; dbg_flags <= flags; end Behavioral;
labcpu/cpualu.vhd
-- ALU -- The ALU uses 1 or 2 operands -- The opcode are bits 14,13,12,11,10 of the instruction -- a: input A of ALU -- b: input B of ALU (not used for single operand instructions) -- q: result (except for compare which is not used) -- f: flag vectors with zero flag, overflow flag, carry flag and sign flag. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cpualu is port ( clk : in STD_LOGIC; rst : in STD_LOGIC; op : in STD_LOGIC_VECTOR(4 downto 0); a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); q : out STD_LOGIC_VECTOR(7 downto 0); f : out STD_LOGIC_VECTOR(3 downto 0) ); end cpualu; architecture Behavioral of cpualu is signal sub : STD_LOGIC_VECTOR(8 downto 0); -- Do subtraction on 9 bits to obtain the carry signal r: STD_LOGIC_VECTOR(7 downto 0); -- ALU result signal zf,ovf,cf,sf : STD_LOGIC; begin --comp_rng: entity work.rng port map(clk=>clk,rst=>rst sub <= ('0'&a) - ('0'&b); r <= a+b when op(4 downto 3)="01" and op(1 downto 0)="00" else sub(7 downto 0) when op(4 downto 3)="01" and op(1 downto 0)="01" else a and b when op(4 downto 3)="01" and op(1 downto 0)="10" else a or b when op(4 downto 3)="01" and op(1 downto 0)="11" else a xor b when op(4 downto 3)="10" and op(1 downto 0)="00" else not a when op(4 downto 0)="11000" else '0'&a(7 downto 1) when op(4 downto 0)="11001" else a(0)&a(7 downto 1) when op(4 downto 0)="11010" else a(7)&a(7 downto 1) when op(4 downto 0)="11011" else a(6 downto 0)&a(7) when op(4 downto 0)="11100" else "00000000"; sf <= sub(7); zf <= not(sub(7) or sub(6) or sub(5) or sub(4) or sub(3) or sub(2) or sub(1) or sub(0)); cf <= sub(8); ovf <= (not a(7) and b(7) and sub(7)) or (a(7) and not b(7) and not sub(7)); f<=zf&ovf&cf&sf; q<=r; end Behavioral;
labcpu/cpuregbank.vhd
-- CPU register banks holding the 4 CPU registers. -- This is used to simplify the reading and writing to registers -- by allowing to address them with a 2-bit address and enable signal. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity cpuregbank is port( clk : in STD_LOGIC; rrd1 : in STD_LOGIC_VECTOR(1 downto 0); rrd2 : in STD_LOGIC_VECTOR(1 downto 0); rwr : in STD_LOGIC_VECTOR(1 downto 0); rwren : in STD_LOGIC; rst : in STD_LOGIC; d : in STD_LOGIC_VECTOR(7 downto 0); q1 : out STD_LOGIC_VECTOR(7 downto 0); q2 : out STD_LOGIC_VECTOR(7 downto 0); -- Only for debugging dbg_qa : out STD_LOGIC_VECTOR(7 downto 0); dbg_qb : out STD_LOGIC_VECTOR(7 downto 0); dbg_qc : out STD_LOGIC_VECTOR(7 downto 0); dbg_qd : out STD_LOGIC_VECTOR(7 downto 0) ); end cpuregbank; architecture Behavioral of cpuregbank is signal enables: STD_LOGIC_VECTOR(3 downto 0); signal qa,qb,qc,qd: STD_LOGIC_VECTOR(7 downto 0); begin ra: entity work.dffre generic map (N=>8) port map(clk=>clk,en=>enables(0),rst=>rst,d=>d,q=>qa); rb: entity work.dffre generic map (N=>8) port map(clk=>clk,en=>enables(1),rst=>rst,d=>d,q=>qb); rc: entity work.dffre generic map (N=>8) port map(clk=>clk,en=>enables(2),rst=>rst,d=>d,q=>qc); rd: entity work.dffre generic map (N=>8) port map(clk=>clk,en=>enables(3),rst=>rst,d=>d,q=>qd); with rwr select enables <= "0001" and rwren&rwren&rwren&rwren when "00", "0010" and rwren&rwren&rwren&rwren when "01", "0100" and rwren&rwren&rwren&rwren when "10", "1000" and rwren&rwren&rwren&rwren when others; with rrd1 select q1 <= qa when "00", qb when "01", qc when "10", qd when others; with rrd2 select q2 <= qa when "00", qb when "01", qc when "10", qd when others; -- Only for debugging dbg_qa <= qa; dbg_qb <= qb; dbg_qc <= qc; dbg_qd <= qd; end Behavioral;
labcpu/cpusequencer.vhd
-- Generates the CPU state sequence seq: ld1 (00), ld2 (01), exec (10) -- Implementation with a D FF with synchronous reset and enable library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity cpusequencer is port( clk : in STD_LOGIC; rst : in STD_LOGIC; en : in STD_LOGIC; seq : out STD_LOGIC_VECTOR(1 downto 0) ); end cpusequencer; architecture Behavioral of cpusequencer is signal s : STD_LOGIC_VECTOR(1 downto 0); begin process(clk,rst) begin if rising_edge(clk) then if rst='1' then s<="00"; else if en='1' then if s="10" then s <= "00"; else s <= s+1; end if; end if; end if; end if; end process; seq <= s; end Behavioral;
labcpu/debounce.vhd
-------------------------------------------------------------------------------- -- -- FileName: debounce.vhd -- Dependencies: none -- Design Software: Quartus II 32-bit Version 11.1 Build 173 SJ Full Version -- -- HDL CODE IS PROVIDED "AS IS." DIGI-KEY EXPRESSLY DISCLAIMS ANY -- WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT -- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A -- PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY -- BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL -- DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF -- PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS -- BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF), -- ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS. -- -- Version History -- Version 1.0 3/26/2012 Scott Larson -- Initial Public Release -- -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY debounce IS GENERIC( counter_size : INTEGER := 19); --counter size (19 bits gives 10.5ms with 50MHz clock) PORT( clk : IN STD_LOGIC; --input clock button : IN STD_LOGIC; --input signal to be debounced result : OUT STD_LOGIC); --debounced signal END debounce; ARCHITECTURE logic OF debounce IS SIGNAL flipflops : STD_LOGIC_VECTOR(1 DOWNTO 0); --input flip flops SIGNAL counter_set : STD_LOGIC; --sync reset to zero SIGNAL counter_out : STD_LOGIC_VECTOR(counter_size DOWNTO 0) := (OTHERS => '0'); --counter output BEGIN counter_set <= flipflops(0) xor flipflops(1); --determine when to start/reset counter PROCESS(clk) BEGIN IF(clk'EVENT and clk = '1') THEN flipflops(0) <= button; flipflops(1) <= flipflops(0); If(counter_set = '1') THEN --reset counter because input is changing counter_out <= (OTHERS => '0'); ELSIF(counter_out(counter_size) = '0') THEN --stable input time is not yet met counter_out <= counter_out + 1; ELSE --stable input time is met result <= flipflops(1); END IF; END IF; END PROCESS; END logic;
labcpu/dffre.vhd
-- 8-bit register (D flip-flop) with synchronous enable and reset library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dffre is generic (N : integer); port( clk : in STD_LOGIC; en : in STD_LOGIC; rst: in STD_LOGIC; d : in STD_LOGIC_VECTOR(N-1 downto 0); q : out STD_LOGIC_VECTOR(N-1 downto 0) ); end dffre; architecture Behavioral of dffre is begin process(clk) begin if rising_edge(clk) then if rst='1' then q<=(others=>'0'); else if en='1' then q<=d; end if; end if; end if; end process; end Behavioral;
labcpu/edgedetect.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity edgedetect is port( clk : in STD_LOGIC; din : in STD_LOGIC; dout : out STD_LOGIC ); end edgedetect; architecture Behavioral of edgedetect is signal last : STD_LOGIC; begin process(clk) begin if rising_edge(clk) then last <= din; end if; end process; dout <= din and not last; end Behavioral;
labcpu/hexto7seg.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use IEEE.std_logic_unsigned.ALL; entity hexto7seg is port( clk: in std_logic; d7: in std_logic_vector(3 downto 0); d6: in std_logic_vector(3 downto 0); d5: in std_logic_vector(3 downto 0); d4: in std_logic_vector(3 downto 0); d3: in std_logic_vector(3 downto 0); d2: in std_logic_vector(3 downto 0); d1: in std_logic_vector(3 downto 0); d0: in std_logic_vector(3 downto 0); blink: in std_logic_vector(7 downto 0); q: out std_logic_vector(6 downto 0); active : out std_logic_vector(7 downto 0) ); end hexto7seg; architecture Behavioral of hexto7seg is signal a: std_logic; signal b: std_logic; signal c: std_logic; signal d: std_logic; signal qt: std_logic_vector(6 downto 0); signal ctr: std_logic_vector(2 downto 0); signal divider: std_logic_vector(25 downto 0); begin p1: process(clk) begin if rising_edge(clk) then divider<=divider+1; end if; end process; p2: process(clk) begin if rising_edge(clk) then if divider(9 downto 0)="0000000000" then ctr<=ctr+1; end if; end if; end process; -- input mux with ctr select a <= d0(3) when "000", d1(3) when "001", d2(3) when "010", d3(3) when "011", d4(3) when "100", d5(3) when "101", d6(3) when "110", d7(3) when others; with ctr select b <= d0(2) when "000", d1(2) when "001", d2(2) when "010", d3(2) when "011", d4(2) when "100", d5(2) when "101", d6(2) when "110", d7(2) when others; with ctr select c <= d0(1) when "000", d1(1) when "001", d2(1) when "010", d3(1) when "011", d4(1) when "100", d5(1) when "101", d6(1) when "110", d7(1) when others; with ctr select d <= d0(0) when "000", d1(0) when "001", d2(0) when "010", d3(0) when "011", d4(0) when "100", d5(0) when "101", d6(0) when "110", d7(0) when others; -- Output mux with ctr select active <= "11111110" when "000", "11111101" when "001", "11111011" when "010", "11110111" when "011", "11101111" when "100", "11011111" when "101", "10111111" when "110", "01111111" when others; -- Blinking q(0) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(0); q(1) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(1); q(2) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(2); q(3) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(3); q(4) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(4); q(5) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(5); q(6) <= (blink(to_integer(unsigned(ctr))) and divider(25)) or qt(6); qt(0) <= not ( (not a and not b and not c and not d ) or (not a and not b and c and not d) or (not a and not b and c and d) or (not a and b and not c and d) or (not a and b and c and not d) or (not a and b and c and d) or (a and not b and not c and not d) or (a and not b and not c and d) or (a and not b and c and not d) or (a and b and not c and not d) or (a and b and c and not d) or (a and b and c and d) ); qt(1) <= not ( (not a and not b and not c and not d) or (not a and not b and not c and d) or (not a and not b and c and not d) or (not a and not b and c and c) or (not a and b and not c and not d) or (not a and b and c and d) or (a and not b and not c and not d) or (a and not b and not c and d) or (a and not b and c and not d) or (a and b and not c and d) ); qt(2) <= not ( (not a and not b and not c and not d) or (not a and not b and not c and d) or (not a and not b and c and d) or (not a and b and not c and not d) or (not a and b and not c and d) or (not a and b and c and not d) or (not a and b and c and d) or (a and not b and not c and not d) or (a and not b and not c and d) or (a and not b and c and not d) or (a and not b and c and d) or (a and b and not c and d) ); qt(3) <= not ((not a and not b and not c and not d) or (not a and not b and c and not d) or (not a and not b and c and d) or (not a and b and not c and d) or (not a and b and c and not d) or (a and not b and not c and not d) or (a and not b and c and d) or (a and b and not c and not d) or (a and b and not c and d) or (a and b and c and not d) ); --qt(4) <= not ((not a and not b and not c and not d) -- or (not a and not b and c and not d) -- or (not a and b and c and not d) -- or (a and not b and not c and not d) -- or (a and not b and c and not d) -- or (a and not b and c and d) -- or (a and b and not c and not d) -- or (a and b and not c and d) -- or (a and b and c and not d) -- or (a and b and c and d) ); --qt(5) <= not ((not a and not b and not c and not d) -- or (not a and b and not c and not d) -- or (not a and b and not c and d) -- or (not a and b and c and not d) -- or (a and not b and not c and not d) -- or (a and not b and not c and d) -- or (a and not b and c and not d) -- or (a and not b and c and d) -- or (a and b and not c and not d) -- or (a and b and c and not d) -- or (a and b and c and d) ); --qt(6) <= not ((not a and not b and c and not d) -- or (not a and not b and c and d) -- or (not a and b and not c and not d) -- or (not a and b and not c and d) -- or (not a and b and c and not d) -- or (a and not b and not c and not d) -- or (a and not b and not c and d) -- or (a and not b and c and not d) -- or (a and not b and c and d) -- or (a and b and not c and d) -- or (a and b and c and not d) -- or (a and b and c and d) ); -- Minimized expression: qt(4) <= not( (a and b) or (a and c) or (c and not d) or (not b and not d) ); qt(5) <= not( (b and not d) or (not a and b and not c) or (a and not b) or (a and c) or (not c and not d) ); qt(6) <= not( (not a and b and not c) or (a and not b) or (a and d) or (not b and c and d) or (c and not d) ); end Behavioral;
labcpu/labcpu.vhd
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity main is Port ( clk : in STD_LOGIC; btnU : in STD_LOGIC; btnD : in STD_LOGIC; btnL : in STD_LOGIC; btnC : in STD_LOGIC; btnR : in STD_LOGIC; btnCpuReset : in STD_LOGIC; sw : in STD_LOGIC_VECTOR (15 downto 0); led : out STD_LOGIC_VECTOR (15 downto 0); seg : out STD_LOGIC_VECTOR(6 downto 0); an : out STD_LOGIC_VECTOR(7 downto 0) ); end main; architecture Structural of main is signal reset : STD_LOGIC; -- clocks signal clkmain : STD_LOGIC; signal clkslow : STD_LOGIC; signal cpu_ram_we : STD_LOGIC; signal cpu_ram_address : STD_LOGIC_VECTOR(4 downto 0); signal cpu_ram_datawr : STD_LOGIC_VECTOR(7 downto 0); signal cpu_ram_datard : STD_LOGIC_VECTOR(7 downto 0); signal ramedit_address : STD_LOGIC_VECTOR(4 downto 0); signal ramedit_data : STD_LOGIC_VECTOR(7 downto 0); signal ramedit_enable : STD_LOGIC; signal ramedit_we : STD_LOGIC; -- Display signals signal display_d7 : STD_LOGIC_VECTOR(3 downto 0); signal display_d6 : STD_LOGIC_VECTOR(3 downto 0); signal display_d5 : STD_LOGIC_VECTOR(3 downto 0); signal display_d4 : STD_LOGIC_VECTOR(3 downto 0); signal display_d3 : STD_LOGIC_VECTOR(3 downto 0); signal display_d2 : STD_LOGIC_VECTOR(3 downto 0); signal display_d1 : STD_LOGIC_VECTOR(3 downto 0); signal display_d0 : STD_LOGIC_VECTOR(3 downto 0); signal display_blink : STD_LOGIC_VECTOR(7 downto 0); signal cpu_d0, cpu_d1, cpu_d2, cpu_d3, cpu_d4, cpu_d5, cpu_d6, cpu_d7 : STD_LOGIC_VECTOR(3 downto 0); -- RAM signals signal ramclk : STD_LOGIC; signal ram_address : STD_LOGIC_VECTOR(4 downto 0); signal ram_datain : STD_LOGIC_VECTOR(7 downto 0); signal ram_we : STD_LOGIC; signal ram_dataout : STD_LOGIC_VECTOR(7 downto 0); -- debouncing signal btnUd,btnDd,btnLd,btnCd,btnRd,btnCpuResetd : STD_LOGIC; signal sw15d,sw13d : STD_LOGIC; -- edge detect signal btnUde,btnDde,btnLde,btnRde : STD_LOGIC; -- Only for CPU debugging signal dbg_qa : STD_LOGIC_VECTOR(7 downto 0); signal dbg_qb : STD_LOGIC_VECTOR(7 downto 0); signal dbg_qc : STD_LOGIC_VECTOR(7 downto 0); signal dbg_qd : STD_LOGIC_VECTOR(7 downto 0); signal dbg_instr : STD_LOGIC_VECTOR(15 downto 0); signal dbg_seq : STD_LOGIC_VECTOR(1 downto 0); signal dbg_flags : STD_LOGIC_VECTOR(3 downto 0); begin -- Debouncing comp_deb1 : entity work.debounce port map(clk=>clk,button=>btnC,result=>btnCd); comp_deb2 : entity work.debounce port map(clk=>clk,button=>btnU,result=>btnUd); comp_deb3 : entity work.debounce port map(clk=>clk,button=>btnD,result=>btnDd); comp_deb4 : entity work.debounce port map(clk=>clk,button=>btnL,result=>btnLd); comp_deb5 : entity work.debounce port map(clk=>clk,button=>btnR,result=>btnRd); comp_deb6 : entity work.debounce port map(clk=>clk,button=>btnCpuReset,result=>btnCpuResetd); comp_deb7 : entity work.debounce port map(clk=>clk,button=>sw(15),result=>sw15d); comp_deb8 : entity work.debounce port map(clk=>clk,button=>sw(13),result=>sw13d); -- Edge detectors on some buttons (for RAM editor) comp_edg1 : entity work.edgedetect port map(clk=>clk,din=>btnLd,dout=>btnLde); comp_edg2 : entity work.edgedetect port map(clk=>clk,din=>btnRd,dout=>btnRde); comp_edg3 : entity work.edgedetect port map(clk=>clk,din=>btnUd,dout=>btnUde); comp_edg4 : entity work.edgedetect port map(clk=>clk,din=>btnDd,dout=>btnDde); -- slow clock -- comp_clk : entity work.clkdiv generic map(N=>25) port map(clkin=>clk,clkout=>clkslow); -- Reset -- reset <= not btnCpuResetd; -- Toggle the RAM edit mode according to sw15d -- ramedit_enable <= sw15d; -- Display debug status on LEDs -- led(15) <= ramedit_enable; led(14) <= clkmain; led(13 downto 12) <= dbg_seq; led(11 downto 8) <= dbg_flags; -- Display multiplexers: toggle between ram edit and cpu mode display_blink <= "00"&ramedit_enable&ramedit_enable&ramedit_enable&ramedit_enable&ramedit_enable&ramedit_enable; display_d7 <= "0000" when ramedit_enable='1' else cpu_d7; display_d6 <= "0000" when ramedit_enable='1' else cpu_d6; display_d5 <= "000"&ram_address(4 downto 4) when ramedit_enable='1' else cpu_d5; display_d4 <= ram_address(3 downto 0) when ramedit_enable='1' else cpu_d4; display_d3 <= sw(7 downto 4) when ramedit_enable='1' else cpu_d3; display_d2 <= sw(3 downto 0) when ramedit_enable='1' else cpu_d2; display_d1 <= ram_dataout(7 downto 4) when ramedit_enable='1' else cpu_d1; display_d0 <= ram_dataout(3 downto 0) when ramedit_enable='1' else cpu_d0; -- Display multiplexers: toggle cpu display modes cpu_d7 <= dbg_qa(7 downto 4); cpu_d6 <= dbg_qa(3 downto 0); cpu_d5 <= dbg_qb(7 downto 4) when sw(14)='1' else "000"&cpu_ram_address(4 downto 4); cpu_d4 <= dbg_qb(3 downto 0) when sw(14)='1' else cpu_ram_address(3 downto 0); cpu_d3 <= dbg_qc(7 downto 4) when sw(14)='1' else dbg_instr(15 downto 12); cpu_d2 <= dbg_qc(3 downto 0) when sw(14)='1' else dbg_instr(11 downto 8); cpu_d1 <= dbg_qd(7 downto 4) when sw(14)='1' else dbg_instr(7 downto 4); cpu_d0 <= dbg_qd(3 downto 0) when sw(14)='1' else dbg_instr(3 downto 0); -- Instantiate the 7-segment display -- comp1: entity work.hexto7seg port map( clk=>clk, d7=>display_d7, d6=>display_d6, d5=>display_d5, d4=>display_d4, d3=>display_d3, d2=>display_d2, d1=>display_d1, d0=>display_d0, blink=>display_blink, q=>seg, active=>an); --comp2: entity work.clkdiv generic map (N => 26) port map( clkin=>clk,clkout=>clkmain ); --led(15)<=clkmain; clkmain <= not ramedit_enable and( (btnCd and not sw13d) or (clkslow and sw13d)); -- Instantiate RAM -- RAM clock is either board clock in edit mode, or manual clock ramclk <= clk when sw15d='1' else clkmain; comp3: entity work.ram generic map(N=>5) port map(clk=>ramclk,address=>ram_address,data=>ram_datain,we=>ram_we,q=>ram_dataout); -- Instantiate the RAM editor comp_ramedit: entity work.ramedit generic map(N=>5) port map(clk=>clk,rst=>reset,btnU=>btnUde,btnD=>btnDde,btnL=>btnLde,btnR=>btnRde,din=>sw, we=>ramedit_we,address=>ramedit_address,data=>ramedit_data); -- Multiplex the editor and the CPU to the RAM -- ram_we <= ramedit_we when ramedit_enable='1' else cpu_ram_we; ram_address <= ramedit_address when ramedit_enable='1' else cpu_ram_address; ram_datain <= ramedit_data when ramedit_enable='1' else cpu_ram_datawr; -- Instantiate the CPU comp_cpu: entity work.CPU generic map(N=>5) port map(clk=>clkmain,rst=>reset,ext_in=>sw(7 downto 0),ext_out=>led(7 downto 0), ram_we=>cpu_ram_we,ram_address=>cpu_ram_address,ram_datawr=>cpu_ram_datawr,ram_datard=>ram_dataout, dbg_qa=>dbg_qa,dbg_qb=>dbg_qb,dbg_qc=>dbg_qc,dbg_qd=>dbg_qd, dbg_instr=>dbg_instr,dbg_seq=>dbg_seq,dbg_flags=>dbg_flags); end Structural;
labcpu/Nexys4_Master.xdc
## This file is a general .xdc for the Nexys4 rev B board ## To use it in a project: ## - uncomment the lines corresponding to used pins ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock signal ##Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ set_property PACKAGE_PIN E3 [get_ports clk] set_property IOSTANDARD LVCMOS33 [get_ports clk] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk] ## Switches #Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0 set_property PACKAGE_PIN U9 [get_ports {sw[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}] #Bank = 34, Pin name = IO_25_34, Sch name = SW1 set_property PACKAGE_PIN U8 [get_ports {sw[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}] #Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2 set_property PACKAGE_PIN R7 [get_ports {sw[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}] #Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3 set_property PACKAGE_PIN R6 [get_ports {sw[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}] #Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4 set_property PACKAGE_PIN R5 [get_ports {sw[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}] #Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5 set_property PACKAGE_PIN V7 [get_ports {sw[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}] #Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6 set_property PACKAGE_PIN V6 [get_ports {sw[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}] #Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7 set_property PACKAGE_PIN V5 [get_ports {sw[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}] #Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8 set_property PACKAGE_PIN U4 [get_ports {sw[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}] #Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9 set_property PACKAGE_PIN V2 [get_ports {sw[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}] #Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10 set_property PACKAGE_PIN U2 [get_ports {sw[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}] #Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11 set_property PACKAGE_PIN T3 [get_ports {sw[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}] #Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12 set_property PACKAGE_PIN T1 [get_ports {sw[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}] #Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13 set_property PACKAGE_PIN R3 [get_ports {sw[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}] #Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14 set_property PACKAGE_PIN P3 [get_ports {sw[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}] #Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15 set_property PACKAGE_PIN P4 [get_ports {sw[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}] ## LEDs #Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0 set_property PACKAGE_PIN T8 [get_ports {led[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] #Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1 set_property PACKAGE_PIN V9 [get_ports {led[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] #Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2 set_property PACKAGE_PIN R8 [get_ports {led[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] #Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3 set_property PACKAGE_PIN T6 [get_ports {led[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] #Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4 set_property PACKAGE_PIN T5 [get_ports {led[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] #Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5 set_property PACKAGE_PIN T4 [get_ports {led[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] #Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6 set_property PACKAGE_PIN U7 [get_ports {led[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] #Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7 set_property PACKAGE_PIN U6 [get_ports {led[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] #Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8 set_property PACKAGE_PIN V4 [get_ports {led[8]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] #Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9 set_property PACKAGE_PIN U3 [get_ports {led[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] #Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10 set_property PACKAGE_PIN V1 [get_ports {led[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] #Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11 set_property PACKAGE_PIN R1 [get_ports {led[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] #Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12 set_property PACKAGE_PIN P5 [get_ports {led[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] #Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13 set_property PACKAGE_PIN U1 [get_ports {led[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] #Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14 set_property PACKAGE_PIN R2 [get_ports {led[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] #Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15 set_property PACKAGE_PIN P2 [get_ports {led[15]}] set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] ##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R #set_property PACKAGE_PIN K5 [get_ports RGB1_Red] #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Red] ##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G #set_property PACKAGE_PIN F13 [get_ports RGB1_Green] #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Green] ##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B #set_property PACKAGE_PIN F6 [get_ports RGB1_Blue] #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Blue] ##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R #set_property PACKAGE_PIN K6 [get_ports RGB2_Red] #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Red] ##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G #set_property PACKAGE_PIN H6 [get_ports RGB2_Green] #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Green] ##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B #set_property PACKAGE_PIN L16 [get_ports RGB2_Blue] #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Blue] ##7 segment display #Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA set_property PACKAGE_PIN L3 [get_ports {seg[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}] #Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB set_property PACKAGE_PIN N1 [get_ports {seg[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}] #Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC set_property PACKAGE_PIN L5 [get_ports {seg[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}] #Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD set_property PACKAGE_PIN L4 [get_ports {seg[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}] #Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE set_property PACKAGE_PIN K3 [get_ports {seg[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}] #Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF set_property PACKAGE_PIN M2 [get_ports {seg[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}] #Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG set_property PACKAGE_PIN L6 [get_ports {seg[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}] ##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP #set_property PACKAGE_PIN M4 [get_ports dp] #set_property IOSTANDARD LVCMOS33 [get_ports dp] #Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0 set_property PACKAGE_PIN N6 [get_ports {an[0]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}] #Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1 set_property PACKAGE_PIN M6 [get_ports {an[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}] #Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2 set_property PACKAGE_PIN M3 [get_ports {an[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}] #Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3 set_property PACKAGE_PIN N5 [get_ports {an[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}] #Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4 set_property PACKAGE_PIN N2 [get_ports {an[4]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}] #Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5 set_property PACKAGE_PIN N4 [get_ports {an[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}] #Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6 set_property PACKAGE_PIN L1 [get_ports {an[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}] #Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7 set_property PACKAGE_PIN M1 [get_ports {an[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}] ##Buttons #Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET set_property PACKAGE_PIN C12 [get_ports btnCpuReset] set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset] #Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC set_property PACKAGE_PIN E16 [get_ports btnC] set_property IOSTANDARD LVCMOS33 [get_ports btnC] #Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU set_property PACKAGE_PIN F15 [get_ports btnU] set_property IOSTANDARD LVCMOS33 [get_ports btnU] #Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL set_property PACKAGE_PIN T16 [get_ports btnL] set_property IOSTANDARD LVCMOS33 [get_ports btnL] #Bank = 14, Pin name = IO_25_14, Sch name = BTNR set_property PACKAGE_PIN R10 [get_ports btnR] set_property IOSTANDARD LVCMOS33 [get_ports btnR] #Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND set_property PACKAGE_PIN V10 [get_ports btnD] set_property IOSTANDARD LVCMOS33 [get_ports btnD] ##Pmod Header JA ##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1 #set_property PACKAGE_PIN B13 [get_ports {JA[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}] ##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2 #set_property PACKAGE_PIN F14 [get_ports {JA[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}] ##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3 #set_property PACKAGE_PIN D17 [get_ports {JA[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}] ##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4 #set_property PACKAGE_PIN E17 [get_ports {JA[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}] ##Bank = 15, Pin name = IO_0_15, Sch name = JA7 #set_property PACKAGE_PIN G13 [get_ports {JA[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}] ##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8 #set_property PACKAGE_PIN C17 [get_ports {JA[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}] ##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9 #set_property PACKAGE_PIN D18 [get_ports {JA[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}] ##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10 #set_property PACKAGE_PIN E18 [get_ports {JA[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}] ##Pmod Header JB ##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1 #set_property PACKAGE_PIN G14 [get_ports {JB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}] ##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2 #set_property PACKAGE_PIN P15 [get_ports {JB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}] ##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3 #set_property PACKAGE_PIN V11 [get_ports {JB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}] ##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4 #set_property PACKAGE_PIN V15 [get_ports {JB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}] ##Bank = 15, Pin name = IO_25_15, Sch name = JB7 #set_property PACKAGE_PIN K16 [get_ports {JB[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}] ##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8 #set_property PACKAGE_PIN R16 [get_ports {JB[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}] ##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9 #set_property PACKAGE_PIN T9 [get_ports {JB[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}] ##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10 #set_property PACKAGE_PIN U11 [get_ports {JB[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}] ##Pmod Header JC ##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1 #set_property PACKAGE_PIN K2 [get_ports {JC[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}] ##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2 #set_property PACKAGE_PIN E7 [get_ports {JC[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}] ##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3 #set_property PACKAGE_PIN J3 [get_ports {JC[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}] ##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4 #set_property PACKAGE_PIN J4 [get_ports {JC[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}] ##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7 #set_property PACKAGE_PIN K1 [get_ports {JC[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}] ##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8 #set_property PACKAGE_PIN E6 [get_ports {JC[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}] ##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9 #set_property PACKAGE_PIN J2 [get_ports {JC[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}] ##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10 #set_property PACKAGE_PIN G6 [get_ports {JC[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}] ##Pmod Header JD ##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1 #set_property PACKAGE_PIN H4 [get_ports {JD[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}] ##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2 #set_property PACKAGE_PIN H1 [get_ports {JD[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}] ##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3 #set_property PACKAGE_PIN G1 [get_ports {JD[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}] ##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4 #set_property PACKAGE_PIN G3 [get_ports {JD[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}] ##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7 #set_property PACKAGE_PIN H2 [get_ports {JD[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}] ##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8 #set_property PACKAGE_PIN G4 [get_ports {JD[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}] ##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9 #set_property PACKAGE_PIN G2 [get_ports {JD[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}] ##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10 #set_property PACKAGE_PIN F3 [get_ports {JD[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}] ##Pmod Header JXADC ##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P #set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] ##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P #set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] ##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P #set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] ##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P #set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] ##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N #set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] ##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N #set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] ##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N #set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] ##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N #set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] ##VGA Connector ##Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0 #set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}] ##Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1 #set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}] ##Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2 #set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}] ##Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3 #set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}] ##Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0 #set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}] ##Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1 #set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}] ##Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2 #set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}] ##Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3 #set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}] ##Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0 #set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}] ##Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1 #set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}] ##Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2 #set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}] ##Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3 #set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}] ##Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS #set_property PACKAGE_PIN B11 [get_ports Hsync] #set_property IOSTANDARD LVCMOS33 [get_ports Hsync] ##Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS #set_property PACKAGE_PIN B12 [get_ports Vsync] #set_property IOSTANDARD LVCMOS33 [get_ports Vsync] ##Micro SD Connector ##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET #set_property PACKAGE_PIN E2 [get_ports sdReset] #set_property IOSTANDARD LVCMOS33 [get_ports sdReset] ##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD #set_property PACKAGE_PIN A1 [get_ports sdCD] #set_property IOSTANDARD LVCMOS33 [get_ports sdCD] ##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK #set_property PACKAGE_PIN B1 [get_ports sdSCK] #set_property IOSTANDARD LVCMOS33 [get_ports sdSCK] ##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD #set_property PACKAGE_PIN C1 [get_ports sdCmd] #set_property IOSTANDARD LVCMOS33 [get_ports sdCmd] ##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0 #set_property PACKAGE_PIN C2 [get_ports {sdData[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}] ##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1 #set_property PACKAGE_PIN E1 [get_ports {sdData[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}] ##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2 #set_property PACKAGE_PIN F1 [get_ports {sdData[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}] ##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3 #set_property PACKAGE_PIN D2 [get_ports {sdData[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}] ##Accelerometer ##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO #set_property PACKAGE_PIN D13 [get_ports aclMISO] #set_property IOSTANDARD LVCMOS33 [get_ports aclMISO] ##Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI #set_property PACKAGE_PIN B14 [get_ports aclMOSI] #set_property IOSTANDARD LVCMOS33 [get_ports aclMOSI] ##Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK #set_property PACKAGE_PIN D15 [get_ports aclSCK] #set_property IOSTANDARD LVCMOS33 [get_ports aclSCK] ##Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN #set_property PACKAGE_PIN C15 [get_ports aclSS] #set_property IOSTANDARD LVCMOS33 [get_ports aclSS] ##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1 #set_property PACKAGE_PIN C16 [get_ports aclInt1] #set_property IOSTANDARD LVCMOS33 [get_ports aclInt1] ##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2 #set_property PACKAGE_PIN E15 [get_ports aclInt2] #set_property IOSTANDARD LVCMOS33 [get_ports aclInt2] ##Temperature Sensor ##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL #set_property PACKAGE_PIN F16 [get_ports tmpSCL] #set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL] ##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA #set_property PACKAGE_PIN G16 [get_ports tmpSDA] #set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA] ##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT #set_property PACKAGE_PIN D14 [get_ports tmpInt] #set_property IOSTANDARD LVCMOS33 [get_ports tmpInt] ##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT #set_property PACKAGE_PIN C14 [get_ports tmpCT] #set_property IOSTANDARD LVCMOS33 [get_ports tmpCT] ##Omnidirectional Microphone ##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK #set_property PACKAGE_PIN J5 [get_ports micClk] #set_property IOSTANDARD LVCMOS33 [get_ports micClk] ##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA #set_property PACKAGE_PIN H5 [get_ports micData] #set_property IOSTANDARD LVCMOS33 [get_ports micData] ##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL #set_property PACKAGE_PIN F5 [get_ports micLRSel] #set_property IOSTANDARD LVCMOS33 [get_ports micLRSel] ##PWM Audio Amplifier ##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM #set_property PACKAGE_PIN A11 [get_ports ampPWM] #set_property IOSTANDARD LVCMOS33 [get_ports ampPWM] ##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD #set_property PACKAGE_PIN D12 [get_ports ampSD] #set_property IOSTANDARD LVCMOS33 [get_ports ampSD] ##USB-RS232 Interface ##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN #set_property PACKAGE_PIN C4 [get_ports RsRx] #set_property IOSTANDARD LVCMOS33 [get_ports RsRx] ##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT #set_property PACKAGE_PIN D4 [get_ports RsTx] #set_property IOSTANDARD LVCMOS33 [get_ports RsTx] ##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS #set_property PACKAGE_PIN D3 [get_ports RsCts] #set_property IOSTANDARD LVCMOS33 [get_ports RsCts] ##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS #set_property PACKAGE_PIN E5 [get_ports RsRts] #set_property IOSTANDARD LVCMOS33 [get_ports RsRts] ##USB HID (PS/2) ##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK #set_property PACKAGE_PIN F4 [get_ports PS2Clk] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk] #set_property PULLUP true [get_ports PS2Clk] ##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA #set_property PACKAGE_PIN B2 [get_ports PS2Data] #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data] #set_property PULLUP true [get_ports PS2Data] ##SMSC Ethernet PHY ##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC #set_property PACKAGE_PIN C9 [get_ports PhyMdc] #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc] ##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO #set_property PACKAGE_PIN A9 [get_ports PhyMdio] #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio] ##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN #set_property PACKAGE_PIN B3 [get_ports PhyRstn] #set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn] ##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV #set_property PACKAGE_PIN D9 [get_ports PhyCrs] #set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs] ##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR #set_property PACKAGE_PIN C10 [get_ports PhyRxErr] #set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr] ##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0 #set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}] ##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1 #set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}] ##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN #set_property PACKAGE_PIN B9 [get_ports PhyTxEn] #set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn] ##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0 #set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}] ##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1 #set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}] ##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK #set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz] #set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz] ##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN #set_property PACKAGE_PIN B8 [get_ports PhyIntn] #set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn] ##Quad SPI Flash ##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK #set_property PACKAGE_PIN E9 [get_ports {QspiSCK}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}] ##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0 #set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}] ##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1 #set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}] ##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2 #set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}] ##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3 #set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}] ##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN #set_property PACKAGE_PIN L13 [get_ports QspiCSn] #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn] ##Cellular RAM ##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK #set_property PACKAGE_PIN T15 [get_ports RamCLK] #set_property IOSTANDARD LVCMOS33 [get_ports RamCLK] ##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN #set_property PACKAGE_PIN T13 [get_ports RamADVn] #set_property IOSTANDARD LVCMOS33 [get_ports RamADVn] ##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN #set_property PACKAGE_PIN L18 [get_ports RamCEn] #set_property IOSTANDARD LVCMOS33 [get_ports RamCEn] ##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE #set_property PACKAGE_PIN J14 [get_ports RamCRE] #set_property IOSTANDARD LVCMOS33 [get_ports RamCRE] ##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN #set_property PACKAGE_PIN H14 [get_ports RamOEn] #set_property IOSTANDARD LVCMOS33 [get_ports RamOEn] ##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN #set_property PACKAGE_PIN R11 [get_ports RamWEn] #set_property IOSTANDARD LVCMOS33 [get_ports RamWEn] ##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN #set_property PACKAGE_PIN J15 [get_ports RamLBn] #set_property IOSTANDARD LVCMOS33 [get_ports RamLBn] ##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN #set_property PACKAGE_PIN J13 [get_ports RamUBn] #set_property IOSTANDARD LVCMOS33 [get_ports RamUBn] ##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT #set_property PACKAGE_PIN T14 [get_ports RamWait] #set_property IOSTANDARD LVCMOS33 [get_ports RamWait] ##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0 #set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}] ##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1 #set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}] ##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2 #set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}] ##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3 #set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}] ##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4 #set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}] ##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5 #set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}] ##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6 #set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}] ##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7 #set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}] ##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8 #set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}] ##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9 #set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}] ##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10 #set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}] ##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11 #set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}] ##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12 #set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}] ##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13 #set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}] ##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14 #set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}] ##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15 #set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}] ##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0 #set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}] ##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1 #set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}] ##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2 #set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}] ##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3 #set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}] ##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4 #set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}] ##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5 #set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}] ##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6 #set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}] ##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7 #set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}] ##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8 #set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}] ##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9 #set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}] ##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10 #set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}] ##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11 #set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}] ##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12 #set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}] ##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13 #set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}] ##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14 #set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}] ##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15 #set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}] ##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16 #set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}] ##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17 #set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}] ##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18 #set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}] ##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19 #set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}] ##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20 #set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}] ##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21 #set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}] ##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22 #set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}] #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}]
labcpu/ram.vhd
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY ram IS generic(N : integer); PORT ( clk: IN std_logic; address: IN STD_LOGIC_VECTOR(N-1 downto 0); data: IN STD_LOGIC_VECTOR(7 downto 0); we: IN std_logic; q: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ram; ARCHITECTURE rtl OF ram IS TYPE mem IS ARRAY(0 TO 2**N-1) OF std_logic_vector(7 DOWNTO 0); SIGNAL ram_block : mem := ( -- Put the initial content of the memory here. Note: provide exactly 32 bytes X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00", X"00" ); BEGIN PROCESS(clk) BEGIN IF rising_edge(clk) THEN IF we = '1' THEN ram_block(to_integer(unsigned(address))) <= data; END IF; END IF; END PROCESS; q <= ram_block(to_integer(unsigned(address))); END rtl;
labcpu/ramedit.vhd
-- RAM editor -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity ramedit is generic(N : integer); port( clk : in STD_LOGIC; rst : in STD_LOGIC; btnU : in STD_LOGIC; btnD : in STD_LOGIC; btnL : in STD_LOGIC; btnR : in STD_LOGIC; din : in STD_LOGIC_VECTOR(15 downto 0); we : out STD_LOGIC; address : out STD_LOGIC_VECTOR(N-1 downto 0); data : out STD_LOGIC_VECTOR(7 downto 0) ); end ramedit; architecture Behavioral of ramedit is -- Register with the address we currently wish to edit signal address_edit : STD_LOGIC_VECTOR(N-1 downto 0); begin process(clk,rst) begin if rising_edge(clk) then if rst='1' then address_edit<=(others=>'0'); else if btnU='1' and btnD='0' then address_edit <= address_edit+1; elsif btnU='0' and btnD='1' then address_edit <= address_edit-1; elsif btnL='1' then address_edit <= din(8+N-1 downto 8); end if; end if; end if; end process; we <= btnR; address <= address_edit; data <= din(7 downto 0); end Behavioral;