1. Truth table and complete Architecture for the D FF with an Enable (En), asynchronies Clr (Clr_Asyn) and synchronize Clr (Clr_syn)?
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY D_Flip_Flop IS
Port (
Clr_syn, Clr_Asyn : IN std_logic; Clk, En : IN std_logic;
D : IN std_logic;
Q : OUT std_logic
);
END D_Flip_Flop;
ARCHITECTURE behavior OF D_Flip_Flop IS signal r_reg , n_reg : std_logic := '0';
begin
process (clk , ) begin
if ( ='1') then
reg <= '0'; elsif (clk'event and clk='1') then
end if;
end process;
reg <= reg;
-----next logic
reg <= D when en='1' else
reg;
----output logic
Q<= reg; end;