HW 5,7
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[IFT 201] |
Computer and Network Systems: Organization and Administration |
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Homework Assignment 5B |
You must show your work to earn points
Score: 30 pts
I. Complete the timing diagrams below for an edge-triggered D Flip Flop (rising edge implied). Assume the output is 0 initially. (3pts*2 = 6 pts)
a. Diagram 1
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b. Diagram 2
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II. For FSMs with the following numbers of states, indicate the smallest possible number of bits for a state register representing those states. (4 pts)
a. 8
b. 9
c. 23
d. 900
III. Design a Moore sequence recognizer that detects the non-overlapping sequence “101”. Use binary encoded state labels and design and draw the circuit schematic similar to the one drawn in class. (7 pts)
V. Reverse engineer the behavior of the sequential circuit shown in the figure below to FSM (follow the steps in the controller design process in reverse). (7 pts)
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