Introduction to digital design Lab task 3
Go ahead and create a new empty project in a new folder as normal. When selecting a device, make sure to specify our specific FPGA model:
Create a "top-level" schematic. Make sure to save it as the same name as what you said would be the "top-level" entity when you created the new project. Also make sure that the schematic is saved in the root directory of your project folder.
New Project Monday, 20 August 2018 5:56 AM
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To effectively use the 50 MHz Quartz Crystal Oscillator, we will use a simple counter symbol in our schematics. Quartus Prime Lite provides a library of parameterized modules (lpm) that we will make use of.
We could find the lpm_counter symbol like normal in the same symbol tool that the logic gates are found, under megafunctions -> arithmetic…. But this method will require you to manually configure all the inputs, outputs and parameters.
A much better way to create our simple counter is to use the IP Catalog wizard. This can be access from the Tools menu.
lpm_counter Monday, 20 August 2018 5:59 AM
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Find and open LMP_CATALOG under the following headings in the IP Catalog: Library -> Basic Functions -> Arithmetic -> LPM_Counter
You will first be asked where to save the new file we are going to create, and the type of file. Select you root folder directory and either VHDL or Verilog as the file type. In this subject we won't be looking at the source code of VHDL or Verilog, either option will work.
Click OK.
The MegaWizard Plug-in Manager will open up. You will be asked how wide the output bus should be. The answer to determine the number of bits depends on the largest number we want to count to or from. For our hardware, we need 26 bits because we need to support counting to or from 50 MHz. 2^26 = 67,108,864.
IP Catalog Monday, 20 August 2018 7:46 AM
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Click Next.
On the next page, you will be asked what type of counter you want. If we leave it in "Plain binary" mode, the counter will count up to 2^26 - 1 = 67,108,863. For this tutorial, we want to generate a periodic frequency of 1 Hz, therefore we want to count up to 49,999,999 from 0. For this reason we select "Modulus" mode and enter a modulus of 50,000,000.
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Click Next.
On the Optional Inputs and EDA pages , we don’t need anything.
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Click Next.
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Click Next.
On the Summary page, we need to make sure we generate the Quartus Prime symbol file.
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Click Finish.
On the last pop-up, click YES to add the file to the project.
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Now that our simple counter symbol has been made, we can place it directly on the top -level schematic.
Open the Symbol Tool like normal and place the symbol.
Using the Symbol Monday, 20 August 2018 8:08 AM
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Open the Symbol Tool again and place one input and one output on the schematic
Use the Orthogonal Bus Tool and draw a short wire from the output of the simple counter. DO NOT connect the wire to anything.
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The wire that we have just connected to the output of the simple counter is actually a "bus line". This means that all 26 outputs [25..0], are represented on that one line. We need to specifically label the line so that we can access each output individually somewhere else on the schematic.
Right click on the drawn output bus line and select properties. Name that bus line "q[25..0]".
Click OK.
Now we will use one of the outputs to flash our LED. Change the name of the output pin to "q[25]". Finally, change the name of the input pin to "clockInput" and connect it to the clock input of the simple counter.
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Save and compile the Project.
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Under the Assignments menu, open Pin Planner.
Change the location of the clockInput Node to PIN_23. Change the location of q[25] Node to PIN_87.
Close the Pin Planner and compile the project.
Pin Planning Monday, 20 August 2018 8:22 AM
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Under the Tools menu, open Programmer.
If you compilation was successful and your USB Blaster is connected to the computer with the drivers installed, you should have the window appear that is shown below:
Programming Monday, 20 August 2018 8:33 AM
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Simply click Start to program you schematic onto the FPGA.
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The output attached to the LED is shown on this image captured from a DSO:
Explain why we have an "On" duty cycle of 32.89 %. Hint: Start by convert 50,000,000 to binary.
Why is this not a problem for "clocking" our circuits?
DSO Analysis Monday, 20 August 2018 9:03 AM
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