ITEC
CHAPTER 7:
The CPU and Memory
The Architecture of Computer Hardware and Systems Software:
An Information Technology Approach
3rd Edition, Irv Englander
John Wiley and Sons 2003
Wilson Wong, Bentley College
Linda Senne, Bentley College
CPU: 3 Major Components
- ALU (arithmetic logic unit)
- Performs calculations and comparisons (data changed)
- CU (control unit): performs fetch/execute cycle
- Functions:
Moves data to and from CPU registers and other hardware components (no change in data)
Accesses program instructions and issues commands to the ALU
- Subparts:
Memory management unit: supervises fetching instructions and data
I/O Interface: sometimes combined with memory management unit as Bust Interface Unit
- Registers
- Example: Program counter (PC) or instruction pointer determines next instruction for execution
System Block Diagram
The Little Man Computer
Concept of Registers
- Small, permanent storage locations within the CPU used for a particular purpose
- Manipulated directly by the Control Unit
- Wired for specific function
- Size in bits or bytes (not MB like memory)
- Can hold data, an address or an instruction
- How many registers does the LMC have?
Registers
- Use of Registers
- Scratchpad for currently executing program
Holds data needed quickly or frequently
- Stores information about status of CPU and currently executing program
Address of next program instruction
Signals from external devices
- General Purpose Registers
- User-visible registers
- Hold intermediate results or data values, e.g., loop counters
- Equivalent to LMC’s calculator
- Typically several dozen in current CPUs
Special-Purpose Registers
- Program Count Register (PC)
- Also called instruction pointer
- Instruction Register (IR)
- Stores instruction fetched from memory
- Memory Address Register (MAR)
- Memory Data Register (MDR)
- Status Registers
- Status of CPU and currently executing program
- Flags (one bit Boolean variable) to track condition like arithmetic carry and overflow, power failure, internal computer error
Register Operations
- Stores values from other locations (registers and memory)
- Addition and subtraction
- Shift or rotate data
- Test contents for conditions such as zero or positive
Operation of Memory
- Each memory location has a unique address
- Address from an instruction is copied to the MAR which finds the location in memory
- CPU determines if it is a store or retrieval
- Transfer takes place between the MDR and memory
- MDR is a two way register
Relationship between MAR,
MDR and Memory
Address
Data
MAR-MDR Example
Visual Analogy of Memory
Individual Memory Cell
Memory Capacity
- Determined by two factors
1. Number of bits in the MAR
LMC = 100 (00 to 99)
2K where K = width of the register in bits
2. Size of the address portion of the instruction
4 bits allows 16 locations
8 bits allows 256 locations
32 bits allows 4,294,967,296 or 4 GB
- Important for performance
- Insufficient memory can cause a processor to work at 50% below performance
RAM: Random Access Memory
- DRAM (Dynamic RAM)
- Most common, cheap
- Volatile: must be refreshed (recharged with power) 1000’s of times each second
- SRAM (static RAM)
- Faster than DRAM and more expensive than DRAM
- Volatile
- Frequently small amount used in cache memory for high-speed access used
ROM - Read Only Memory
- Non-volatile memory to hold software that is not expected to change over the life of the system
- Magnetic core memory
- EEPROM
- Electrically Erasable Programmable ROM
- Slower and less flexible than Flash ROM
- Flash ROM
- Faster than disks but more expensive
- Uses
BIOS: initial boot instructions and diagnostics
Digital cameras
Fetch-Execute Cycle
- Two-cycle process because both instructions and data are in memory
- Fetch
- Decode or find instruction, load from memory into register and signal ALU
- Execute
- Performs operation that instruction requires
- Move/transform data
LMC vs. CPU
Fetch and Execute Cycle
Load Fetch/Execute Cycle
| PC -> MAR | Transfer the address from the PC to the MAR |
| MDR -> IR | Transfer the instruction to the IR |
| IR(address) -> MAR | Address portion of the instruction loaded in MAR |
| MDR -> A | Actual data copied into the accumulator |
| PC + 1 -> PC | Program Counter incremented |
Store Fetch/Execute Cycle
| PC -> MAR | Transfer the address from the PC to the MAR |
| MDR -> IR | Transfer the instruction to the IR |
| IR(address) -> MAR | Address portion of the instruction loaded in MAR |
| A -> MDR* | Accumulator copies data into MDR |
| PC + 1 -> PC | Program Counter incremented |
| *Notice how Step #4 differs for LOAD and STORE |
ADD Fetch/Execute Cycle
| PC -> MAR | Transfer the address from the PC to the MAR |
| MDR -> IR | Transfer the instruction to the IR |
| IR(address) -> MAR | Address portion of the instruction loaded in MAR |
| A + MDR -> A | Contents of MDR added to contents of accumulator |
| PC + 1 -> PC | Program Counter incremented |
LMC Fetch/Execute
SUBTRACT
PC MAR
MDR IR
IR[addr] MAR
A – MDR A
PC + 1 PC
IN
PC MAR
MDR IR
IOR A
PC + 1 PC
OUT
PC MAR
MDR IR
A IOR
PC + 1 PC
HALT
PC MAR
MDR IR
BRANCH
PC MAR
MDR IR
IR[addr] PC
BRANCH on Condition
PC MAR
MDR IR
If condition false: PC + 1 PC
If condition true: IR[addr] PC
Bus
- The physical connection that makes it possible to transfer data from one location in the computer system to another
- Group of electrical conductors for carrying signals from one location to another
- Line: each conductor in the bus
- 4 kinds of signals
Data (alphanumeric, numerical, instructions)
Addresses
Control signals
Power (sometimes)
Bus
- Connect CPU and Memory
- I/O peripherals: on same bus as CPU/memory or separate bus
- Physical packaging commonly called backplane
- Also called system bus or external bus
- Example of broadcast bus
- Part of printed circuit board called motherboard that holds CPU and related components
Bus Characteristics
- Protocol
- Documented agreement for communication
- Specification that spells out the meaning of each line and each signal on each line
- Throughput, i.e., data transfer rate in bits per second
- Data width in bits carried simultaneously
Point-to-point vs. Multipoint
Broadcast bus Example: Ethernet
Plug-in device
Shared among multiple devices
Motherboard
- Printed circuit board that holds CPU and related components including backplane
Typical PC Interconnections
Bus interface bridges connect different bus types
PCI Bus Connections
Instructions
- Instruction
- Direction given to a computer
- Causes electrical signals to be sent through specific circuits for processing
- Instruction set
- Design defines functions performed by the processor
- Differentiates computer architecture by the
Number of instructions
Complexity of operations performed by individual instructions
Data types supported
Format (layout, fixed vs. variable length)
Use of registers
Addressing (size, modes)
Instruction Elements
- OPCODE: task
- Source OPERAND(s)
- Result OPERAND
- Location of data (register, memory)
Explicit: included in instruction
Implicit: default assumed
Addresses
OPCODE
Source
OPERAND
Result
OPERAND
Instruction Format
- Machine-specific template that specifies
- Length of the op code
- Number of operands
- Length of operands
Simple
32-bit Instruction Format
Instruction Formats: CISC
Instruction Formats: RISC
Instruction Types
- Data Transfer (load, store)
- Most common, greatest flexibility
- Involve memory and registers
- What’s a word ? 16? 32? 64 bits?
- Arithmetic
- Operators + - / * ^
- Integers and floating point
- Logical or Boolean
- Relational operators: > < =
- Boolean operators AND, OR, XOR, NOR, and NOT
- Single operand manipulation instructions
- Negating, decrementing, incrementing
More Instruction Types
- Bit manipulation instructions
- Flags to test for conditions
- Shift and rotate
- Program control
- Stack instructions
- Multiple data instructions
- I/O and machine control
Register Shifts and Rotates
Program Control Instructions
- Program control
- Jump and branch
- Subroutine call
and return
Stack Instructions
- Stack instructions
- LIFO method for organizing information
- Items removed in the reverse order from that in which they are added
Push
Pop
Fixed Location Subroutine
Return Address Storage: Oops!
Stack Subroutine Return Address Storage
Multiple Data Instructions
- Perform a single operation on multiple pieces of data simultaneously
- SIMD: Single Instruction, Multiple Data
- Intel MMX: 57 multimedia instruction
- Commonly used in vector and array processing applications
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