Analog Digital Electronics

ARL1

ASSIGNMENT #2 OCTOBER 2017 201CDE – ANALOG AND DIGITAL ELECTRONICS

(ADE)

1. Solve the following problems:

a. Simplify the following Boolean function using algebraic manipulation:

X’YZ + X’YZ’ + XZ 3 Marks

b. Prove the identity of the following Boolean function using

algebraic manipulation: A’B’C’D’ + A’B’CD’ + AB’C’D’ + AB’CD’ = B’D’

3 Marks

c. Simplify the given expression to its Sum of Products (SOP) form using Boolean postulates. Draw the logic circuit for the simplified SOP function

Y = (A + B) (A + (AB)’) C + A’(B + C’ ) + AB + ABC

5 Marks

d. Minimize the logic function 𝑌(𝐴,𝐵,𝐶,𝐷) = ∑(0,1,2,3,5,7,8,9,11,14) by using Karnaugh Map. Draw logic circuit for the simplified function.

5 Marks

2. Draw the state diagram for the Table 1 below that describes a finite- state machine which has one input x and one output z

Present

State

Next State Output (z)

x = 0 x = 1 x = 0 x = 1

A A E 1 0

B C F 0 0

C B H 0 1

D E F 0 0

E D A 0 1

F B F 1 1

G D H 0 1

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H H G 1 0

Table 1 6 Marks

3. Design two State Diagrams, each for Mealy and Moore machines, for

a sequence detector that outputs a 1 when it detects the final bit in the serial data stream, “1101.”

10 Marks

4. Consider the following state diagram in Figure 1 for a synchronous

circuit with one input X and one output Z. Analyze this state diagram and draw its circuit implementation using JK flip-flop (state Q0) and T flip-flop (state Q1) and MUX-4x1 for Z

Figure 1

25 Marks

5. Consider the following clocked sequential circuit in Figure 2, with one input (X) and one output (Z):

Figure 2

a. Drive a state table and draw a state diagram for the circuit 8 Marks

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b. Redesign this circuit by replacing the Q1 flip-flop (i.e. the D flip-

flop holding Q1 state) with a JK flipflop, and the Q2 flip-flop with

a T flip-flop. Only show the excitation equations (or state

equations) for J1, K1, and T2 10 Marks

c. Use MULTISIM to verify the function of the designed circuit in

Part(b)

10 Marks

6. Write a Behavioral VHDL description for a 4-bit shift register. The shift

register is to be negative edge triggered. Sin is a serial input to the

most significant bit of the shift register. Sout is a serial output from

the least significant bit of the shift register. En_n is an active low

enable. sreg is the 4-bit register. Write only the VHDL ENTITY and

ARCHITECTURE construct. 15 Marks

END OF PAPER