Verilog HDL code

2017/10/1 Isidore : 17_FA_ECE_444_01 : Class Material

https://isidore.udayton.edu/portal/site/51491abb-7fc6-4217-9f5d-82e031ef32a0/tool/ac011e6f-8073-43e2-aba4-6376c1941443/ShowItem?returnVi… 1/1

Instructions Design a "FIFO" memory system with the following characteristics:

- Two commands: "enqueue" and "dequeue" - Enqueue loads the data in the location immediately following the previous data load

- Dequeue removes the data at the "head of the line." - FIFO memory structure should allow modlar expansion

Implement as a parameterized design in terms of word length and the number of words in the memory. Hint: Use small numbers for the parameters to speed compilation and ease the testing of the logic.

Implement two versions:

- In one, use the VERILOG memory declaration - In the other, use a memory wizard (NOT THE FIFO WIZARD)

Compare the performance of your designs with the FIFO that can be generated using the FIFO WIZARD.