JOURNAL PAPER

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016 459

Iterative Gain Enhancement in an Algorithmic ADC Timothy A. Monk, Paul J. Hurst, Fellow, IEEE, and Stephen H. Lewis, Fellow, IEEE

Abstract—This paper presents a 14.9-bit 3.57-MS/s algorithmic ADC that uses iterative gain enhancement, a technique that uses multiple clock phases to increase the effective op-amp gain in a switched-capacitor circuit. Using an op-amp that gives only 30-dB loop gain in a feedback circuit without gain enhancement, ap- plication of the iterative gain enhancement technique boosts the loop gain to 81 dB. The algorithmic ADC uses a capacitor sharing and scaling technique, which saves power and reduces errors. The ADC has an active area of 0.75 mm2 in 0.25-μm CMOS and dis- sipates 16.2 mW. Iterative gain enhancement increases the SNDR from 44.6 dB to 78.5 dB and the SFDR from 45.9 dB to 96.2 dB. Reducing the number of gain-enhancement iterations for the LSBs increases the conversion rate from 3.57 MS/s to 4.65 MS/s with only minor performance degradation.

Index Terms—Analog-to-digital converter, CMOS operational amplifier, switched-capacitor circuits.

I. INTRODUCTION

S WITCHED-capacitor (SC) circuits are commonly used inapplications such as data conversion and filtering. As tech- nology becomes more advanced, fT increases, which makes op-amps faster. However, more advanced processes also give reduced intrinsic transistor gain, and this trend increases errors in feedback circuits. A common technique to achieve high gain is to add cascodes, but that leads to reduced signal swing, which is a problem with the low power supplies required for more advanced processes. Multi-stage amplifiers can increase gain without reducing swing, but require additional power.

Early SC gain-enhancement techniques increased effective loop gain, but used only one level of gain enhancement. Initial approaches [1], [2] use a capacitor to subtract the voltage at the op-amp input associated with the previous sample from the op-amp input. These approaches reduce the error at the virtual ground node, enhancing the gain for low-frequency signals where two consecutive output samples have similar values, which is the case in low-pass SC filters. Correlated dou- ble sampling (CDS) [3], [4] generalized previous techniques,

Manuscript received September 29, 2015; revised December 19, 2015; accepted January 4, 2016. Date of publication March 4, 2016; date of current version April 15, 2016. This research was supported by Analog Devices, Northrop Grumman, the Agilent Foundation, and NSF Grant 1444086. Chip fabrication was donated by Intersil. This paper was recommended by Associate Editor A. M. A. Ali.

T. A. Monk was with the Solid-State Circuits Research Laboratory, Department of Electrical and Computer Engineering, University of California, Davis, CA 95616 USA. He is now with Silicon Laboratories, Inc., Nashua, NH 03062-5737 USA.

P. J. Hurst and S. H. Lewis are with the Solid-State Circuits Research Laboratory, Department of Electrical and Computer Engineering, University of California, Davis, CA 95616 USA (e-mail: hurst@ucdavis.edu).

Digital Object Identifier 10.1109/TCSI.2016.2528081

enhancing the gain by using an additional clock phase to estimate the output, during which the op-amp input is sampled. The extra clock phase increases settling time, because addi- tional capacitance must charge to the output voltage. Several techniques [5]–[8] eliminate the speed penalty in pipelined ADCs by processing the signal [5] or error [8] in a parallel path, or by using time interleaving [6], [7]. CDS techniques all have additional noise from the switched capacitor that performs the subtraction at the op-amp input. Also, all these techniques except for [8] give less gain enhancement as output amplitudes increase, since the op-amp still produces the entire output and the op-amp gain falls as its output approaches the swing limits. This reduced gain affects the amount of gain enhancement achieved for large output amplitudes.

The sample-and-hold amplifier (SHA) in [9] uses an addi- tional capacitor to sample the input and then switches it in series with the op-amp output. Because an SHA has a gain of one, the voltage sampled on this capacitor is ideally equal to the desired output, ignoring errors associated with sampling. As a result, placing this capacitor in series with the op-amp output allows the op-amp to produce only a small output voltage in practice, reducing the gain error compared to a conventional SHA and achieving enhanced op-amp gain. Correlated level shifting (CLS) [10] uses the same principle with an added estimation phase that generates an output voltage sampled by a level-shifting capacitor. Thus, CLS can be used in most SC circuits. CLS provides many advantages over CDS. It has less added noise, because the capacitor used for gain enhancement is at the op-amp output. The feedback network is the same in the estimation and output phases, so extra capacitors that need to be charged are not required. Therefore, although extra clock phases are used, extra time is not required for settling. CLS enhances gain with rail-to-rail output swing, since the amplifier output voltage is small during the output phase. However, the level-shifting capacitor is in series with the capacitive output load, and this series connection introduces a voltage divider that reduces the loop gain during the output phase. Also, CLS cannot drive resistive loads because a capacitor is in series with the amplifier output. Finally, because CLS operates at the op- amp output, it does not reduce offset and flicker noise as CDS does. In [11] and [12], different op-amp structures are used during the estimation phase and output phase, each optimized for the requirements during one phase. In [13], CLS is applied multiple times using multiple level-shifting capacitors, allow- ing for signal swing beyond the power supply, but reducing accuracy compared to [10]. An alternative to gain enhancement is to replace a conventional op-amp with an unconventional circuit that can function like a high-gain op-amp [12], [14], but their effective-number-of-bit (ENOB) performance has been limited to less than 12 bits.

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460 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016

Fig. 1. Switched-capacitor (SC) amplifier (a) without and (b) with estimated output added.

In this paper, multiple iterations of gain enhancement are used to increase the effective gain more than can be achieved with a single iteration. This work uses a gain-enhancement method similar to [15], which adds less noise than CDS, but requires some extra power to bias additional active circuitry. Unlike CLS, the gain-enhancement method presented here does not achieve full rail-to-rail output swing, but is capable of driving resistive loads.

To demonstrate iterative gain enhancement, a two-stage 1.5-bit-per-stage algorithmic ADC was designed, fabricated and tested. The operation is similar to a pipelined ADC, except instead of always passing a residue to the next stage, residues pass back and forth between two stages until the desired number of bits are resolved. With sufficient digital redundancy, the accuracy of the ADC is determined by the gain accuracy of the residue amplifiers and not by comparator offsets. The residue amplifier is a SC amplifier, and its gain accuracy depends on the loop gain of the residue amplifier. The accuracy of the residue amplifier can be quantified by ADC performance measures such as SNDR and SFDR, which are roughly proportional to the loop gain of the residue amplifier, until approaching a limit set by the resolution of the ADC. This work uses iterative gain enhancement in the residue amplifier to increase its effective loop gain, which increases its gain accuracy.

In this paper, Section II introduces iterative gain enhance- ment. Section III presents techniques used in the algorithmic ADC. Section IV describes the prototype ADC. Section V gives measured results. Section VI concludes the paper.

II. ITERATIVE GAIN ENHANCEMENT

A. Gain Enhancement Principle

Fig. 1(a) shows the switched-capacitor feedback amplifier used as the residue amplifier in this work. First, during φ1, the input is sampled onto both CS and CF . Then, during φ2, the capacitors are connected to ground and the output as shown. Ideally, the op-amp forces the inverting-opamp-input voltage

vE to ground, moving the charge from CS onto CF . Then the output voltage vO is equal to the desired output voltage vO,des

vO,des =

( 1 +

CS CF

) vIN. (1)

However, in practice vO contains an error that depends on the loop gain T and the desired output voltage, and it is given by

vO =

( 1 +

CS CF

) vIN

( 1 −

1

T + 1

) (2)

vO = vO,des − vO T︸︷︷︸

error

(3)

where

T = bA. (4)

Here b is the feedback factor and, ignoring parasitic capaci- tances, is given by

b = CF

CF + CS . (5)

Increasing op-amp gain increases the loop gain and reduces the error in (3); however, as process and power supplies scale, achieving high op-amp gain becomes difficult.

An alternative way to reduce the magnitude of vE in Fig. 1(a) during φ2 is to reduce the output of the amplifier A by adding an estimate of the voltage the output is trying to reach, v̂O, as shown in Fig. 1(b). The output voltage of this circuit is

vO = vO,des − vX T︸︷︷︸

error

. (6)

Now the error is proportional to vX instead of vO. Therefore, since vX is the difference between vO and v̂O, the error is reduced to the extent that v̂O is approximately equal to the desired output during φ2. The effective loop gain Teff with gain enhancement is defined to be the loop gain that would give the same gain error in the conventional op-amp feedback circuit in Fig. 1(a), which is described by (2). Therefore, for gain- enhanced circuits, the effective loop gain can be found using

vO = vO,des

( 1 −

1

Teff + 1

) . (7)

B. Iterative Gain Enhancement

Fig. 2 shows the concept of the proposed iterative gain enhancement applied to the SC amplifier in Fig. 1(a). The gain- enhanced op-amp is enclosed in a dashed box, and it includes a conventional gain stage A followed by capacitors CA − CC and associated switches that implement the gain enhancement.

It uses an active summer, so that the output vO is the sum of the voltages on capacitors CA, CB and CC . φ2 is divided into three sub-phases: φA, φB , and φC , as shown in Fig. 3. During φ1, the input is sampled onto CS and CF as before, and voltages vA, vB, and vC are set to 0. During φA, the φ2,

MONK et al.: ITERATIVE GAIN ENHANCEMENT IN AN ALGORITHMIC ADC 461

Fig. 2. Iterative gain enhancement in a SC amplifier.

Fig. 3. Clocks for iterative gain enhancement.

and φA switches are closed and an initial output is produced using the top signal path through the φA switch, with vB and vC connected to ground. The output at the end of φA (or at time tA) is given by

vO(tA) = vO,des

( 1 −

1

TA + 1

) . (8)

Since gain enhancement is not used yet, the effective loop gain is the loop gain TA during φA. After φA ends, CA holds the voltage vX generated during φA, and that held voltage contributes to the output voltage vO during the following sub- phases. During φB , the φA switch is open and the φB switch closes, switching in the second signal path, and the output voltage is

vO(tB) = vO(tA)

TB + 1 + vO,des

TB TB + 1

. (9)

Combining (8) and (9) gives

vO(tB) = vO,des

( 1 −

1

(TA + 1)(TB + 1)

) . (10)

Because the amplifier now only needs to produce an output vX that is the difference between vO and vA, the magnitude of the amplifier output voltage vX is smaller than during φA. Comparing (7) and (10) shows that the effective loop gain at the end of φB is Teff ≈ TATB. During φC , CB holds vX from φB while the third path is switched in, so the output voltage is

vO(tC) = vO,des

( 1 −

1

(TA + 1)(TB + 1)(TC + 1)

) . (11)

The voltages on CA and CB together generate an estimated output that is a better estimate of vO than the estimate generated during φA. The magnitude of vX during φC is smaller than

Fig. 4. Iteratively gain-enhanced op-amp.

during φB , so the effective loop gain during φC is higher than during φB. Comparing (7) and (11) gives

Teff ≈ TATBTC. (12)

In principle, φ2 could be divided into more sub-phases with more parallel paths, but only three sub-phases are used here. The reason for this choice is explained in Section II-D.

While Fig. 2 shows the amplifier output being sampled and then summed, this need not be the case. Previous SC gain enhancement techniques have sampled the op-amp input [1]–[4], the op-amp output [10], [13], or the first-stage output in a two-stage op-amp [15], [16]. In the approach presented here, the output of the first stage of a two-stage op-amp is sampled, similar to [15], but parallel second stages are used to simplify biasing and to allow more than one iteration of gain enhancement, as described in detail in Section II-C.

C. Iteratively Gain-Enhanced Op-Amp

Fig. 4 shows about half of the differential two-stage op- amp with iterative gain enhancement. For simplicity, the part of the second stage producing the negative output and common- mode feedback are not shown. Three parallel common-source amplifiers MA, MB, and MC implement the gain enhancement by converting the voltages vA, vB , and vC from the three parallel paths into currents and adding the currents at the output. Although the parallel output resistances of MA, MB, and MC reduce the gain, gain enhancement more than makes up for this reduction. The gate capacitances of MA and MB in Fig. 4 act as CA and CB in Fig. 2, and they hold the sampled values of vX . Before the gate of MB or MC connects to the output of the first stage, it connects to a bias voltage VB3, which is equal to the common-mode output voltage of the first stage and is generated by a replica of the first stage. When a gate is connected to VB3, that device does not contribute to the signal at the op- amp output. During φA, φB , or φC , only one of transistors MA, MB, and MC is connected to vX . The open-loop gain A of the op-amp during φA is

A = A1 gmARo. (13)

Here A1 is the gain of the first stage, gmA is the transcon- ductance of MA, and Ro is the output resistance of the three second stages in parallel. The gain A during φB or φC is found

462 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016

Fig. 5. Inter-stage (a) switches and (b) clocks.

by replacing gmA with the transconductance of MB during φB or MC during φC . From (4), (12) and (13)

Teff ≈ b3A31 gmA gmB gmCR 3 o. (14)

The effective loop gain is proportional to the product of the transconductances of the second stage devices MA, MB, and MC. To assure that the DC biasing is the same during all sub- phases, MA-MC have equal DC gate-to-source voltages, hence they have equal overdrive voltages. Therefore, the transconduc- tance of each of MA, MB, and MC is proportional to its drain current. For a given transistor length and total current flowing through these transistors, the sum of the widths of these tran- sistors and Ro of the amplifier are determined. From (14), the effective loop gain is proportional to the product of the drain currents in these transistors, and the maximum effective loop gain for a given total current is achieved when the currents are equal. Therefore, to maximize the effective loop gain in (14), the second-stage devices MA, MB, and MC are matched. Also, in practice, the gain of the second stages falls as its output approaches the swing limits, so in practice each gmRo term in (14) is not constant. For gain enhancement, each bA1gmRo term in (14) must be greater than one. In the prototype ADC, to assure this is the case, the op-amp output swings were chosen so that all transistors that connect to vO+ are in saturation at the output-swing limits.

For maximum gain enhancement with linear op-amp settling, all the sub-phase clocks φA − φC should have equal high times. This gives the op-amp equal time to settle in each sub-phase, so any decrease in accuracy due to incomplete settling is the same in each sub-phase. In the presence of slewing, however, giving more high time to φA than to φB or φC increases the maximum gain enhancement by allowing the op-amp output to slew and settle before the end of the first sub-phase. Simulations and measurements indicate that allocating half of φ2 to φA, and splitting the remaining half equally between φB and φC works well. Because the times allocated to φ2, φA, and φB are related by factors of two, the logic to generate these clocks is simple.

D. Interstage Switches

Fig. 5 shows the interstage switches used for iterative gain enhancement that are shown in Fig. 4 in more detail as well as the associated clocks. The clock signals are not to scale. Charge injection from switches S1 and S2 turning off alters vA and vB, introducing errors in the sampled values of vX . The charge-

injection error can be separated into two components: constant or offset errors and gain errors. The offset errors caused by charge injection do not appear in the differential output due to the fully differential architecture of the op-amp. However, the gain error from charge injection does appear in the differential output. Such gain error modifies the effective loop gains TA and TB in (12). (Note that the final output is generated when φc is high, so charge injection from the switch controlled by φc is not an issue.) To reduce this gain error, dummy charge cancellation switches are included [17]. All the transistors in Fig. 5 are small to limit the charge injection not cancelled by the dummy switches. However, the switches cannot be made too small; otherwise, the pole created by a switch’s on-resistance and the gate capacitance of MA, MB, or MC may reduce the phase margin of the op-amp. Simulations indicated that the dummy switches reduced the gain error stemming from charge injec- tion. However, the performance of the prototype was measured only with the dummy switches. Since the performance was not also measured without the dummy switches, the prototype testing does not prove that the dummy switches were helpful.

In our design, MA, MB, and MC are identical and should match well, and the switches associated with each common- source amplifier are also identical. Thus, the added pole is about constant during each sub-phase. Therefore, a fixed frequency- compensation network can be used, which consists of transistor MR in triode and CM , as shown in Fig. 4. If different sized MA, MB, and MC or switches were used, the frequency- compensation network would have to be designed to compen- sate the worst case.

The clocks labeled φA, φAB , and φR in Fig. 5 are delayed complements of φA, φAB, and φR so that the charge cancella- tion switches do not turn on until after the corresponding main switches turn off. Also, φC is a delayed complement of φC , ensuring that MC in Fig. 4 is not connected to both vX and VB3 before φ2 falls during φC .

During a short reset phase φR between sub-phases, a switch shorts the differential outputs of the first stage to reset the first- stage outputs. Without this reset, at the start of φB or φC , the capacitance at the output of the first stage would initially keep vX unchanged from the previous sub-phase. Then the op-amp would initially try to drive its output vO to the wrong voltage, causing an undesired transient at the start of each sub-phase that would increase the time needed to settle. The reset reduces the settling time by eliminating this transient in the op-amp output at the start of a sub-phase due to an initially incorrect first-stage output voltage driving MB or MC. While φR must not overlap with the falling edge of φA or φB, it does overlap the rising edge of φB and φC . During the overlap, the gain of first stage is reduced temporarily.

E. Added Noise

The extra circuitry added to implement iterative-gain en- hancement adds noise in two ways. First, each of the second gain stages in the op-amp contributes its own noise, tripling the noise power from the second stage. When this noise is input referred, however, it is small, as long as the gain of the first stage is significantly greater than one.

MONK et al.: ITERATIVE GAIN ENHANCEMENT IN AN ALGORITHMIC ADC 463

Fig. 6. Two-stage algorithmic ADC. (a) Sampling. (b) Generating odd residues. (c) Generating even residues.

Second, each MOS switch that connects to vX generates noise when it is on. Initially, consider the switch in Fig. 4 that connects vX to vA when φA goes high. During φA, the thermal noise from that switch affects the op-amp output vO+. Consider only this noise source. While that switch is on, the magnitude of the transfer function from that thermal voltage noise source to vA at low frequencies is 1/(1 + TA), which is small. The transfer-function magnitude increases as the op-amp gain rolls off, and then falls at high frequencies due to a pole formed by the on resistance of this switch and the capacitance at the gate of MA. The noise at vA is sampled and held on the capacitance at the gate of MA when φA goes low. During φB , the gain magnitude from vA to vO+ is equal to the gain magnitude of the second stage |A2| = gmARo divided by 1 + TB, so the noise in vO+ due to the noise sample at vA is less during φB than φA. During φC , the noise in vO+ due to the noise sample at vA is reduced by 1/(1 + TC) due to feedback. Therefore, the contri- bution to vO+ from the noise sample at vA is small during φC .

When φB is high, the switch controlled by φB generates thermal noise. Now, consider only this noise source. While that switch is on, the magnitude of the transfer function from that thermal voltage noise source to vB is 1/(1 + TB) at low frequencies and varies with frequency, similar to the description above. The noise at vB is sampled on the capacitance at the gate of MB when φB goes low. During φC , the gain from vB to vO+ is equal to A2/(1 + TC). Therefore the contribution of this noise source to vO+ is reduced by feedback during φB and φC .

Finally, the switch controlled by φC generates noise in vO+ that is also reduced by feedback during φC . The final output is generated during φC when that switch is on; no sampling is involved here. In our simulations, these added noise terms were all negligible compared to other noise sources.

III. ALGORITHMIC ADC ARCHITECTURE

A. Two-Stage Algorithmic ADC

While algorithmic ADCs are area efficient, they are not very power efficient, because they cannot employ scaling as easily as pipelined ADCs. The operation of a conventional two-stage algorithmic ADC is shown in Fig. 6. Each stage consists of an op-amp, two capacitors, an analog-to-digital sub-converter (ADSC) and a digital-to-analog sub-converter (DASC). Capac- itors C1 and C2 belong to stage 1, while C3 and C4 belong

Fig. 7. Two-stage algorithmic ADC with op-amp sharing and capacitor sharing and scaling.

to stage 2. First, stage 1 samples and partially quantizes the input in Fig. 6(a) and then produces the first residue, while stage 2 samples and quantizes that residue in Fig. 6(b). Then stage 2 produces the second residue, while stage 1 samples and quantizes that residue in Fig. 6(c). Because C1 and C2 are large to limit thermal noise when sampling the ADC input, the second stage has to drive a large capacitive load. Therefore, the second-stage op-amp is not scaled down to save power. How- ever, one op-amp can be shared between the two stages [18]. While the residue appears between the op-amp output and ground, it also appears across the feedback capacitor, since the op-amp input is a virtual ground. The next section describes a technique that takes advantage of this fact to reduce the capacitive load on the op-amp, thereby also reducing op-amp power dissipation.

B. Capacitor Sharing and Scaling

To improve power efficiency, this work combines op-amp sharing with a capacitor sharing technique (shown in Fig. 7 in [19]) and a capacitor scaling technique [20]. The proposed approach is shown in Fig. 7. The schematics shown here are single ended; the actual implementation is fully differential. First, all four capacitors sample the input and produce the first residue. This provides one level of capacitor scaling, as the sampling capacitance is doubled compared to the conventional case, which reduces the thermal noise when the ADC samples the input. Since the first residue voltage appears across C3 and C4 while they are in feedback around the op-amp and since they are used to produce the second residue, a load capacitor is not connected from the op-amp output to ground in Fig. 7(b). Therefore, the capacitive load on the op-amp output is smaller than in a conventional algorithmic ADC when the first residue is produced. Until the ADC takes a new sample of the ADC input vIN, the two stages share C4, which is always in feedback, while C1 and C3 switch roles as load and input capacitors. Using only one load capacitor during each of these phases reduces the op- amp load. In this way, capacitor scaling and sharing together

464 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016

Fig. 8. Residue plots for (a) a typical 1.5-bit stage, (b) reference voltage scaling, and (c) this work.

decrease the op-amp load during the entire conversion process, thus reducing the op-amp power required for a given thermal noise specification.

Additionally, sampling the residue on the feedback capacitor instead of a load capacitor increases the accuracy of the sam- pled residue [21] and reduces the effects of offset and op-amp noise. This is because the sampled residue voltage is referenced to the op-amp input instead of ground, so the error in the voltage across the feedback capacitor is smaller than the error in the op-amp output voltage. For a feedback factor of 1/2, the error across the feedback capacitor is half the error at the op- amp output. Sampling the residue on the feedback capacitor translates into an increase in the effective loop gain of 6 dB and a 50% reduction in offset and op-amp noise in the residue. For later residues, half the residue is sampled on the feedback capacitor and half on the load capacitor, so the error is the average of the errors on these two capacitors. For a feedback factor of 1/2, the error in the residue fed to the next stage is 3/4 of the error at the op-amp output, which is the average of half of the error at the op-amp output sampled on the feedback capacitor and all of the error at the op-amp output sampled on the load capacitor. In this case, the effective loop gain increases by 2.5 dB and the offset and op-amp noise decrease by 25% in the residue.

C. Reference Voltage Scaling

To improve the signal-to-noise ratio (SNR), some reference voltage scaling [22] is used. The residue plot of a conventional 1.5-bit stage is shown in Fig. 8(a). The gray area shows the valid input and output ranges and is square because these ranges are identical.

Reference voltage scaling increases the reference voltage of the ADC, but the peak residue voltage produced by a stage is unchanged because it is limited by the output swing of the op-amp. If the reference voltage is doubled as proposed in [22], the input range increases by only a factor of 1.5 to maintain the same output range, as shown in Fig. 8(b). The gray area showing valid input and output ranges is now rectangular instead of square and no longer contains the entire residue plot; thus, some codes are never excited or produced by the ADC. Doubling the reference voltage causes the residue to jump from one side of the allowed output range to the other at the com- parator thresholds, leaving no room to handle increased residue amplitudes arising from comparator and amplifier offsets. To avoid this problem, the reference voltage is instead increased by some factor less than 2 in practice.

Fig. 9. Reduced number of iterations for LSBs.

In this work, the power supply voltage is 2.5 V, and the fully differential op-amp has an output range of about ±2.2 V. With- out reference scaling, the input range and reference voltage would both be ±2.2 V. To avoid having a reference that exceeds the supply, the reference is set to 2.5 V, so it only increases by 14% (from 2.2 V to 2.5 V) in this work. To limit the residue output to 2.2 V, the peak input increases by only 7% (from 2.2 V to 2.35 V), as shown in Fig. 8(c). Therefore, about 2000 codes at the ends of the input-output characteristic are never excited, about 6% of the codes in a 15-bit output, resulting in 14.9-bit resolution.

With fewer codes excited, the maximum signal-to- quantization-noise ratio decreases with reference scaling. However, the SNR of an ADC is usually limited by some other noise source that does not change when the reference voltage increases. In this case, the increase in the peak input allowed by reference voltage scaling increases the maximum SNR by a factor of 1.07, or about 0.6 dB.

D. Reduced Iterations for LSBs

The conversion rate of an algorithmic ADC with iterative gain enhancement can be increased by reducing the number of gain-enhancement iterations when resolving the least signifi- cant bits (LSBs), similar to [23], [24]. This reduction is possible because errors in later stages are less significant than those in earlier stages, since the errors in each stage are input referred by dividing by the residue-amplifier gains of all the previous stages. Fewer sub-phases for iterative gain enhancement for the LSBs means less time spent resolving the LSBs, and the result is a higher conversion rate for the algorithmic ADC.

As pictured in Fig. 9, this work uses two iterations for the first five residues, one iteration for residues six through eight, and no iterations for the remaining residues. Measurements show that reducing iterations in this way does not significantly affect performance. In this timing diagram, TR is the time to generate a residue when two iterations of gain enhancement are used. With one iteration of gain enhancement, the time to generate the residue decreases by 25 percent. With no gain enhancement iterations, the time to generate the residue is cut in half. The clocks needed in Fig. 9 can be generated without the need for a PLL or DLL, as required in [24], since clock edges are already available at the appropriate times. Using the clocking shown in Fig. 9 results in a 30% increase in the ADC conversion rate. When using fewer iterations of gain enhancement in later residues, multiple common-source devices can be connected in parallel to boost the gm and increase the loop gain. Because the gain increase is in the second stage, the Miller capacitance

MONK et al.: ITERATIVE GAIN ENHANCEMENT IN AN ALGORITHMIC ADC 465

Fig. 10. Die photo.

also increases and the op-amp remains stable. In the prototype, MA and MC are both connected to vX for the last residues that use no gain enhancement. The wiring of the switches in Fig. 5 does not allow MA and MB to be connected to vX at the same time (if φA and φB are both high, the gate of MB would be simultaneously connected to vX and bias voltage VB3). However, if the switch network was redesigned, then MB could also be connected to vX during φA when one and no iterations of gain enhancement are used.

IV. PROTOTYPE ADC IMPLEMENTATION

A prototype algorithmic ADC was built in a 1P3M 0.25-μm CMOS process. The analog circuits are fully differential, and the ADC outputs 15 bits. Fig. 10 shows a die photo of the proto- type algorithmic ADC. The ADC occupies an area of 0.75 mm2, including on-chip logic that generates the clocks for the ADC and the iterative gain enhancement. This logic generates all the clocks necessary for ADC operation and two iterations of gain enhancement based on two clock inputs: a 100-MHz clock, which is divided by four internally, sets the stage rate and a 3.57-MHz clock sets the conversion rate and resolution of the ADC. This conversion rate is equal to the stage clock rate of 25 MHz divided by 7, which is the number of cycles required to generate the complete digital output. With additional external clocks, the on-chip logic allows the ADC to operate with either 0, 1, or 2 iterations of gain enhancement. However, in all cases, all the analog gain-enhancement circuits (i.e. MA, MB, and MC) are biased on, degrading the loop gain and consuming some power. Using external clocks, the ADC can also operate with a reduced number of gain enhancement iterations for just the LSBs as described in Section III-D.

Because the gain enhancement does not correct for mismatch in the feedback network, good capacitor matching is necessary for good performance. With careful layout, capacitor matching to a 15-bit level is possible [25]. Each capacitor in the ADC is 0.5 pF, and each capacitor consists of four 125-fF MIM unit capacitors arranged in a common-centroid configuration. Additionally, each unit capacitor uses a 3D-matching structure based on the version 2 layout in [26], adjusted because the

Fig. 11. Output spectra for (a) 0, (b) 1, and (c) 2 iterations of gain enhancement.

bottom plates of the capacitors are not connected together for the algorithmic ADC architecture used in this work.

V. EXPERIMENTAL RESULTS

Unless stated otherwise, a 2.5 V supply was used to collect data. The reference voltage is 2.5 V, and the input range is ±2.35 V. Fig. 11 shows a set of plots of measured ADC output spectra with 0, 1, and 2 iterations of gain enhancement for a full-scale sinusoidal input at 100 kHz. Without gain enhance- ment, harmonic distortion due to residue amplifier gain errors limits the SNDR to 44.6 dB, SFDR to 45.9 dB and THD to −44.7 dB. With one iteration of gain enhancement, harmonic distortion decreases to −66.1 dB but still limits the SNDR to 65.7 dB and the SFDR to 69.4 dB. With two iterations of gain enhancement, harmonic distortion decreases to −88.7 dB, and the SNDR is noise limited. The corresponding SNDR and SFDR are 78.5 dB and 96.2 dB, respectively.

For comparison, the prototype was operated from a 2 V supply. Without gain enhancement, the SNDR is 46.6 dB, and the SFDR is 49.7 dB. With one iteration of gain enhancement, the SNDR is 62.8 dB, and the SFDR is 66.8 dB. With two iter- ations of gain enhancement, the SNDR and SFDR are 74.2 dB and 84.7 dB, respectively. Therefore, the gain enhancement significantly improves performance when the supply is reduced to 2 V, but not as much as when the supply is 2.5 V.

Fig. 12 shows plots of SNDR versus conversion rate when 0, 1, and 2 iterations of gain enhancement are used. The input is about 1 dB below full scale. As the conversion rate increases, the time available for op-amp settling decreases, and incomplete settling eventually degrades performance. As the

466 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016

Fig. 12. SNDR vs. conversion rate.

Fig. 13. INL for (a) 0, (b) 1, and (c) 2 iterations of gain enhancement.

number of gain enhancement iterations decreases, the ADC’s SNDR drops, but is about constant to higher conversion rates because with fewer iterations used, the duration of each sub- phase increases at a given conversion rate. However, even without enough time for complete settling in each sub-phase, at 4–8 MS/s, gain enhancement still improves performance. Simulations indicate that the peaking in the SNDR with 1 and 2 iterations of gain enhancement is due to overshoot during op-amp settling, which is sampled at the end of the first sub- phase and is equivalent to having a higher loop gain there.

Fig. 13 shows plots of INL for 0, 1 and 2 iterations of gain enhancement. Fig. 14 shows plots of DNL for 0, 1, and 2 itera- tions of gain enhancement. Only 30 800 codes appear because voltage reference scaling is used, as described in Section III-C. The corresponding resolution is 14.9 bits (= log2 30, 800). The measured INL indicates that the capacitor matching was almost good enough for 15-bit performance, but testing of more prototype chips would be needed to determine whether this performance can be reliably reproduced. Fig. 15 shows plots of SFDR and SNDR versus input frequency for two iterations of gain enhancement. The input is about 1 dB below full scale. SNDR degrades by less than 3 dB for input frequencies up to 2 MHz. For higher input frequencies, the linearity of

Fig. 14. DNL for (a) 0, (b) 1, and (c) 2 iterations of gain enhancement.

Fig. 15. SNDR and SFDR vs. input frequency.

Fig. 16. SNDR vs. input amplitude.

the input switches limit performance. Fig. 16 shows plots of SNDR versus input amplitude for 0, 1 and 2 iterations of gain enhancement with a 50-kHz sinusoidal input. The last data point on each plot is for an input amplitude 0.1 dB above full scale. Since the plot for 2 iterations of gain enhancement is a straight line for amplitudes less than full scale, the SNDR is noise limited in this case. Dynamic range is about 80 dB.

Fig. 17 compares the output spectrum with two iterations of gain enhancement applied to all residues to the output spectrum with a reduced number of iterations for the LSBs as described in Section III-D. In Fig. 17(a), the conversion rate is 3.57 MS/s.

MONK et al.: ITERATIVE GAIN ENHANCEMENT IN AN ALGORITHMIC ADC 467

Fig. 17. Output spectra for (a) 2 iterations of gain enhancement for all bits using external clocking, with fS = 3.57 MS/s and (b) a reduced number of gain-enhancement iterations for LSBs, with fS = 4.65 MS/s.

TABLE I POWER DI S S I PATION

Reducing the number of iterations for the LSBs increases the conversion rate to 4.65 MS/s in Fig. 17(b) with only minor performance degradation. Both plots use the same frequency scale so harmonics of the 100 kHz input can be compared easily. Because the on-chip logic does not generate the clocks necessary for the mode with a reduced number of iterations for the LSBs, external clocking is used for both cases. [Thus the plot in Fig. 17(a) is different than the plot in Fig. 11(c)]. This is done in order to make a fair comparison, as performance is worse when using external clocking. These results show that the conversion rate can be increased by 30 percent when using a reduced number of iterations of gain enhancement for the LSBs.

Table I shows total ADC power dissipation for the four modes of operation considered: 0, 1 and 2 iterations of gain enhancement, as well as using a reduced number of gain- enhancement iterations for the LSBs. Analog power dissipation is approximately constant in all modes at about 13 mW. Digital power is 2.3 mW for no gain enhancement and increases by about 0.5 mW for each iteration of gain enhancement added. This increase stems from extra switching to increase the number of gain-enhancement iterations. With a reduced number of iterations for the LSBs (case R.I. in the table), the power dissipation remains approximately the same as the 2 iteration case, at 16.2 mW. While the increased conversion rate here increases the digital power dissipation, the decreased switching when resolving the LSBs reduces the digital power dissipation, resulting in almost no change in the total power dissipation.

Fig. 18. SFDR versus loop gain (from simulation).

TABLE II EFFECTI VE GAI N

TABLE III PERF ORMANCE SUMMARY

The residue amplifier in the ADC is a SC amplifier, and its gain accuracy depends on the loop gain of the residue amplifier. The accuracy of the residue amplifier can be quantified by ADC performance measures such as SNDR and SFDR, which are functions of the loop gain of the residue amplifier. Here, SFDR is used to estimate the effective loop gain with iterative gain enhancement. The algorithmic ADC architecture used in this work was simulated in MATLAB, including an op-amp with finite gain and parasitic input capacitance. The simulation result, SFDR versus loop gain, is plotted in Fig. 18. The plotted line has a slope of about one, so the SFDR of the ADC is approximately proportional to the loop gain in the range plotted. This plot and the measured SFDR allow calculation of the effective loop gain for 0, 1, and 2 iterations of gain enhancement as shown in Table II. Effective loop gain increases from 30 dB with no gain enhancement to 54 dB with one iteration and to 81 dB with two iterations. Because the feedback capacitors are twice as large when producing the first residue as when producing the other residues, the feedback factor is not constant. The average feedback factor is 0.37. Therefore, the effective open-loop op-amp gain is about 39 dB with no gain enhancement, 63 dB with one iteration, and 90 dB with two iterations.

468 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 63, NO. 4, APRIL 2016

TABLE IV FOM COMPARI S ON WI TH PI P ELI NES

Table III summarizes the measured performance of the pro- totype ADC for 0, 1, and 2 iterations of gain enhancement in all stages, as well as in the mode with a reduced number of gain- enhancement iterations for the LSBs. Iterative gain enhance- ment dramatically improves the linearity of the ADC. The table also compares performance against some other algorithmic ADCs. At the bottom of the table, a figure of merit (FOM) is listed [30]–[32]. This FOM is appropriate for this work, as the prototype’s SNDR exceeds 75 dB, where designs are usually limited by thermal noise [33]. Power efficiency can be improved by reducing the number of gain-enhancement iterations for the LSBs, as shown by the larger FOM in that mode.

Table IV compares the measured performance of some pipelined ADCs to a projected pipelined version of the proto- type ADC. The assumption for the projected prototype is that the circuitry is repeated 7 times and reconfigured to give a pipelined converter, which is 7 times faster than the algorithmic ADC and has the same SNDR performance as the prototype algorithmic ADC. Therefore, the power dissipation and sam- pling frequency both increase by a factor 7, so the FoM for the projected pipeline version of the prototype is the same as the FoM for the prototype algorithmic ADC. (We selected the FoM for the reduced number of iterations version, R.I., for this comparison.) The larger number of pipelined ADCs compared to algorithmic ADCs makes this a worthwhile comparison. The projected ADC is competitive with other ADCs.

VI. CONCLUSION

Iterative gain enhancement is a technique that increases the effective loop gain of op-amp-based circuits. It was used in an algorithmic ADC and achieved higher effective loop gain than previous techniques. Using an op-amp that gives only 30-dB loop gain in a residue-amplifier feedback circuit without gain enhancement, application of the iterative gain enhancement technique boosts the effective loop gain to 81 dB. Capacitor sharing and scaling are used to reduce the power dissipated by the algorithmic ADC. This reduction allows algorithmic ADCs to be used in applications where small area and low power are required. A prototype ADC was built in 0.25-μm CMOS and achieves 78.5-dB SNDR at 3.57 MS/s while dissipating 16.2 mW.

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Timothy A. Monk received the B.S. degree from the University of Maine, Orono, ME, USA, in 2005, and the M.S and Ph.D. degrees from the University of California at Davis, CA, USA, in 2010 and 2012, respectively. In 2013, he joined Silicon Laboratories, Inc., Nashua, NH, USA, where he is involved in the design of analog and mixed-signal integrated circuits.

Paul J. Hurst (S’76–M’83–SM’94–F’01) received the B.S., M.S., and Ph.D. degrees in electrical engi- neering from the University of California at Berkeley, CA, USA, in 1977, 1979, and 1983, respectively.

From 1983 to 1984, he was with the Univer- sity of California, Berkeley, as a Lecturer, teaching integrated-circuit design courses and working on an MOS delta-sigma modulator. In 1984, he joined Silicon Systems Inc., Nevada City, CA, where he was involved in the design of CMOS integrated circuits for voice-band modems. Since 1986, he has been on

the faculty of the Department of Electrical and Computer Engineering at the University of California at Davis, CA, USA, where he is now a Professor. His research interests are in the areas of data converters and analog and mixed- signal integrated-circuit design for digital communications.

Prof. Hurst has served on the program committees for the Symposium on VLSI Circuits and the International Solid-State Circuits Conference. He has served as an associate editor for the JOURNAL OF SOLI D-STATE CI RCUI TS and as a member of the administrative committee of the IEEE Solid-State Circuits Society. He is a coauthor of a textbook on analog integrated-circuit design. He is also active as a consultant to industry.

Stephen H. Lewis (S’85–M’88–SM’97–F’01) re- ceived the B.S. degree from Rutgers University, New Brunswick, NJ, USA, in 1979, the M.S. degree from Stanford University, Stanford, CA, USA, in 1980, and the Ph.D. degree from the University of California at Berkeley, CA, USA, in 1987, all in elec- trical engineering. From 1980 to 1982, he was with Bell Laboratories in Whippany, NJ, USA, where he was involved in circuit design for magnetic recording. In 1988, he rejoined Bell Laboratories in Reading, PA, USA, where he concentrated on the design of

analog-to-digital converters. In 1991, he joined the Department of Electrical and Computer Engineering, University of California, Davis, CA, USA, where he is now a professor. He is a coauthor of a college textbook on analog integrated circuits, and his research interests include data conversion, signal processing, and analog circuit design.