ET220 : Module 1 Introduction to Digital Technology

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Name:

 

 

 

Date:

 

 

 

Grade:

 

 

Instructions:

 

  • Complete Part 1, then Part 2 sections of the Lab 1.1.  Then, complete this Lab Report by filling in all details.  Use information you gained during your experimentation to complete the answers.

  • Be sure to submit your lab report before the deadline.

     

 

Part 1- Binary-to-Decimal Number Conversion

 

Theory:

 

  1. Enter the decimal, hexadecimal, and BCD numbers for each of the following binary numbers.

 

Binary

Hexadecimal

BCD

Decimal

0000

 

 

 

0001

 

 

 

0010

 

 

 

0011

 

 

 

0100

 

 

 

0101

 

 

 

0110

 

 

 

0111

 

 

 

1000

 

 

 

1001

 

 

 

1010

 

 

 

1011

 

 

 

1100

 

 

 

1101

 

 

 

1110

 

 

 

1111

 

 

 

 

  1. Explain major differences between binary and BCD numeric representations.

     

 

Planning:

 

  1. Provide a list of places that you can obtain the datasheets for the following components:

 

  • SN74LS47  Binary to BCD Decoder

  • MAN72 Seven Segment Display

  • 4116R 1-331 330 ohm Resistor Pack

 

 

 

Preparation:

 

2.       Why is it important to follow ESD safety procedures when handling electronic components? What are some of the main considerations?

 

 

 

Wiring Procedure:

 

3.       Complete the wiring diagram.  Refer to Lab 1.1 Figure 1-4 and image 1 & 2 of the ET1220.U1.Lab.Images PowerPoint.  Use MS Paint to complete the wiring diagram.

 

 

 

 

 

 

Test Procedure:

 

4.       Record the observed values from Lab 1.1 Table 1-1.  Indicate which segments are illuminated for each input setting.

 

Inputs

Output

 

Binary

Data Lines

BCD Number

Seven Segment Display

 

 

3

2

1

0

 

 

 

0

0

0

0

 

 

0

0

0

1

 

 

0

0

1

0

 

 

0

0

1

1

 

 

0

1

0

0

 

 

0

1

0

1

 

 

0

1

1

0

 

 

0

1

1

1

 

 

1

0

0

0

 

 

1

0

0

1

 

 

1

0

1

0

Invalid

 

1

0

1

1

Invalid

 

1

1

0

0

Invalid

 

1

1

0

1

Invalid

 

1

1

1

0

Invalid

 

1

1

1

1

Invalid

 

 

 

 

 

 

Troubleshooting:

 

5.       For each trouble investigated, record your observations from Lab 1.1 Table 1-2. 

 

Trouble

Trouble

Observations

1

LED for the C segment is open. Break the connection to pin C of the 7-segment display (remove the wire).

 

2

An input to the 7447 is open. Break the connection to the input A pin of the 7447 (remove the wire).

 

3

1000 ohm resistor is open. (Remove the 1kΩ resistor).

 

 

 

 

6.       Assume that the switches are set to a binary 1000 value, but the display shows a zero.  What are three possible causes for this error?

 

 

 

 

 

 

 

Part 2- Binary-Number Addition and Two’s Complement Subtraction

 

Theory:

 

  1. Provide the results for the half-adder truth table.

     

     

 

A0

+

B0

S1S0

0

+

0

 

0

+

1

 

1

+

0

 

1

+

1

 

 

 

 

 

 

  1. Provide the results for the full-adder truth table.

 

 

 

 

 

 

A0

+

B0

+

Cin

CoutS

0

+

0

+

0

 

1

+

0

+

0

 

0

+

1

+

0

 

0

+

0

+

1

 

1

+

1

+

0

 

1

+

0

+

1

 

0

+

1

+

1

 

1

+

1

+

1

 

 

 

 

Planning:                                                  

 

  1. Provide a list of places (links) where you can obtain the datasheets for the following components:

 

    • 74LS08 Quad AND Gate

    • 74LS32 Quad OR Gate

    • 74LC86 Quad XOR Gate

       

      Preparation:

  1. What are several important things you should consider before wiring your circuit? 

 

 

 

Wiring Procedure:

 

  1. Complete the adder wiring diagram.  Refer to Lab 1.1 Figure 1-12 and image 10 of the ET1220.U1.Lab.Images PowerPoint.  Use MS Paint to complete the wiring diagram.

 

 

 

 

Test Procedure:

 

  1. Record the observed values from Lab 1.1 Table 1-3. 

 

Switch

 

Switch

 

 

 

4

3

Decimal Value of B

2

1

Decimal Value of A

 

 

B1

B0

A1

A0

Calculated

Sum

7-Segment

Display

0

0

0

0

0

0

0

0

0

0

0

0

1

1

 

 

0

0

0

1

0

2

 

 

0

0

0

1

1

3

3

 

0

1

1

0

0

0

 

 

0

1

1

0

1

1

 

 

0

1

1

1

0

2

 

 

0

1

1

1

1

3

4

 

1

0

2

0

0

0

 

 

1

0

2

0

1

1

 

 

1

0

2

1

0

2

 

 

1

0

2

1

1

3

5

 

1

1

3

0

0

0

 

 

1

1

3

0

1

1

 

 

1

1

3

1

0

2

 

 

1

1

3

1

1

3

 

 

 

 

 

 

 

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  • lab_1.1_report.docx